diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-07-15 19:02:22 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-09 14:41:52 +0000 |
| commit | 1f88a71aa8dd950b62556bd421dcf5edf3c01f9a (patch) | |
| tree | 9abf973862780d1ad30fef33dab465e50d294799 | |
| parent | 5eb5f863b5f7cf24b991755ee1216023a55cd673 (diff) | |
soc/intel/alderlake: Enable Irms UPD for ADL
This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit
is set to non zero. It results VR TDC Input current to be treated as it
is root mean square.
This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit
for TdcEnable UPD.
BRANCH=None
TEST=Build and boot brya with debug FSP and verify Irms UPD value
from logs
Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
| -rw-r--r-- | src/soc/intel/alderlake/vr_config.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 88a0c31225..ab84c15a94 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -88,8 +88,6 @@ void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, s_cfg->IccMax[domain] = cfg->icc_max; s_cfg->TdcTimeWindow[domain] = cfg->tdc_timewindow; s_cfg->TdcCurrentLimit[domain] = cfg->tdc_currentlimit; - if (cfg->tdc_timewindow != 0 && cfg->tdc_currentlimit != 0) - s_cfg->TdcEnable[domain] = 1; } else { uint16_t mch_id = 0; @@ -110,7 +108,12 @@ void fill_vr_domain_config(FSP_S_CONFIG *s_cfg, s_cfg->TdcCurrentLimit[domain] = load_table(vr_config_tdc_currentlimit, ARRAY_SIZE(vr_config_tdc_currentlimit), domain, mch_id); - if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) - s_cfg->TdcEnable[domain] = 1; + } + + /* Check TdcTimeWindow and TdcCurrentLimit, + Set TdcEnable and Set VR TDC Input current to root mean square */ + if (s_cfg->TdcTimeWindow[domain] != 0 && s_cfg->TdcCurrentLimit[domain] != 0) { + s_cfg->TdcEnable[domain] = 1; + s_cfg->Irms[domain] = 1; } } |