diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-05-07 00:59:32 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-08 15:28:41 +0000 |
| commit | 1efa7d90933e64e309c79fe1f9aa3f3033930e0e (patch) | |
| tree | 7a94ac7375f6a1c2467a2527e68c1e89f75f9944 | |
| parent | 6cd6e71b71d4314bfc3dd8aeccc3f5c3c6364c13 (diff) | |
sb/intel/bd82x6x: Put temp BAR in a define
We use a temporary BAR value to program the thermal settings. To make
this more obvious, factor it out.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Icda6e4100d954fe28d2624270b5d7ab7ed155e32
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_thermal.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index e73f3a5908..60c08d136d 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -22,6 +22,9 @@ static uint16_t read16p (uintptr_t addr) return read16((u16 *)addr); } +/* Temporary address for the thermal BAR */ +#define TBARB_TEMP 0x40000000 + /* Early thermal init, must be done prior to giving ME its memory which is done at the end of raminit. */ void early_thermal_init(void) @@ -32,31 +35,31 @@ void early_thermal_init(void) dev = PCI_DEV(0x0, 0x1f, 0x6); /* Program address for temporary BAR. */ - pci_write_config32(dev, 0x40, 0x40000000); + pci_write_config32(dev, 0x40, TBARB_TEMP); pci_write_config32(dev, 0x44, 0x0); /* Activate temporary BAR. */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); + write16p(TBARB_TEMP + 0x04, 0x3a2b); - write16p(0x40000004, 0x3a2b); - write8p(0x4000000c, 0xff); - write8p(0x4000000d, 0x00); - write8p(0x4000000e, 0x40); - write8p(0x40000082, 0x00); - write8p(0x40000001, 0xba); + write8p(TBARB_TEMP + 0x0c, 0xff); + write8p(TBARB_TEMP + 0x0d, 0x00); + write8p(TBARB_TEMP + 0x0e, 0x40); + write8p(TBARB_TEMP + 0x82, 0x00); + write8p(TBARB_TEMP + 0x01, 0xba); /* Perform init. */ /* Configure TJmax. */ msr = rdmsr(MSR_TEMPERATURE_TARGET); - write16p(0x40000012, ((msr.lo >> 16) & 0xff) << 6); + write16p(TBARB_TEMP + 0x12, ((msr.lo >> 16) & 0xff) << 6); /* Northbridge temperature slope and offset */ - write16p(0x40000016, 0x808c); + write16p(TBARB_TEMP + 0x16, 0x808c); - write16p(0x40000014, 0xde87); + write16p(TBARB_TEMP + 0x14, 0xde87); /* Enable thermal data reporting, processor, PCH and northbridge */ - write16p(0x4000001a, (read16p(0x4000001a) & ~0xf) | 0x10f0); + write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0); /* Disable temporary BAR */ pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); |