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authorLean Sheng Tan <sheng.tan@9elements.com>2022-09-07 16:07:33 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-09-30 16:50:38 +0000
commit1ec8f97782060757dc8d2df2ff1c022039b225f8 (patch)
treecd0c75e355d023056b0923f086ebf37ee53f36ba
parent7c3e48c5734aa3b5482bd36244d6c3b4a187eb3a (diff)
soc/intel/adl: Add config option to enable FSP-S SATA test mode
For further info on SATA test mode, please refer to this doc: https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/sata-mqst-setup-paper.pdf Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I6ef79fc5723348d5fd10b2ac0847191fa4f37f41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67410 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/alderlake/Kconfig6
-rw-r--r--src/soc/intel/alderlake/fsp_params.c2
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index c79eb08c7b..a73657ee2c 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -317,6 +317,12 @@ config SOC_INTEL_ALDERLAKE_S3
help
Select if using S3 instead of S0ix to disable D3Cold.
+config ENABLE_SATA_TEST_MODE
+ bool "Enable test mode for SATA margining"
+ default n
+ help
+ Enable SATA test mode in FSP-S.
+
config SOC_INTEL_UART_DEV_MAX
int
default 7
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 016d8ad3ab..5346403705 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -757,6 +757,8 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
* these disable variables to 1 in devicetree overrides.
*/
s_cfg->SataPwrOptEnable = !(config->sata_pwr_optimize_disable);
+ /* Test mode for SATA margining */
+ s_cfg->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE);
/*
* Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
* SataPortsDmVal is the DITO multiplier. Default is 15.