diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-02-25 10:07:10 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-29 20:59:15 +0100 |
| commit | 1e67106001cd9a2fa98ba45f361a3f85135fbe1e (patch) | |
| tree | 5a8405c5bbb3047ad1bbf87e5b8345881d51148f | |
| parent | 4815fb8dc5eb7b44bc8aa2a981c6a6bee55fa5c7 (diff) | |
google/chell: Update DPTF configuration
Update the DPTF configuration for the chell mainboard:
1) Enable DPTF charger control, set max current to 1975mA
according to the battery specification.
2) Enable charger effect on charger temp sensor in TRT
3) Set PL2 to 15W which is the same value configured in the CPU.
BUG=chrome-os-partner:49859,chrome-os-partner:50306
BRANCH=glados
TEST=build and boot on chell
Change-Id: I644256b9596cc5295513c48f5e3a18e6ce8b0a6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c19740a227f932bf80e9243341ec81763779719c
Original-Change-Id: Icff5edc9d659bea6370ff8de1334ebf0983340da
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329187
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13842
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/mainboard/google/chell/acpi/dptf.asl | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/chell/acpi/dptf.asl index c8362b7c28..d3549a73df 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/chell/acpi/dptf.asl @@ -37,12 +37,21 @@ #define DPTF_TSR3_PASSIVE 55 #define DPTF_TSR3_CRITICAL 70 -/* SKL-Y EC already has a custom charge profile based on temperature. */ -#undef DPTF_ENABLE_CHARGER - /* SKL-Y is Fanless design. */ #undef DPTF_ENABLE_FAN_CONTROL +/* Enable DPTF charger control */ +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x7b7, "mA", 0 }, /* 1975mA (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1500mA */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0mA */ +}) + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, @@ -56,6 +65,9 @@ Name (DTRT, Package () { /* CPU Effect on Temp Sensor 2 */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 }, + /* CPU Effect on Temp Sensor 3 */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, }) @@ -73,8 +85,8 @@ Name (MPPC, Package () }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */ |