diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2022-06-28 18:26:37 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-30 16:29:06 +0000 |
| commit | 1cb77d1425ac3594eb27d05f5acfa58ed2501c27 (patch) | |
| tree | 9b2d4af6b9e8f4691264525f6a7bf9b0926bdfe2 | |
| parent | f35c074ad4dc1916496b13524f6b453ef5cf2635 (diff) | |
mb/google/brya/var/gimble: Disable PCH USB2 phy power gating
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237421399
TEST=Verify the build for gimble board
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie66c9679c985215ad7f1a5ae76560b839ea95702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65474
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/overridetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 07458e9a8d..a149c33101 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -31,6 +31,10 @@ chip soc/intel/alderlake register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[1]" = "USB2_PORT_MAX_TYPE_C(OC1)" # set MAX to USB2_C1 for eye diagram register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2 |