diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2022-02-25 09:20:14 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2022-03-30 14:59:55 +0000 |
| commit | 1c27671504c1e2cb4a3d858bf2ce1a946f9c8cdb (patch) | |
| tree | 543ce91343e92f49029d21f6000904c433d5282d | |
| parent | 51a43f922c65d65fb6d8a8c99f6310bc7f863304 (diff) | |
mb/google/cherry: Add PCIe domain support for dojo
Add override device tree for dojo and add PCIe domain support.
Reference:
- MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
| -rw-r--r-- | src/mainboard/google/cherry/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/variants/dojo/overridetree.cb | 22 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index 51ad029db3..206c4e41f0 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -71,4 +71,7 @@ config CHERRY_USE_MAX98390 endchoice +config OVERRIDE_DEVICETREE + default "variants/dojo/overridetree.cb" if BOARD_GOOGLE_DOJO + endif diff --git a/src/mainboard/google/cherry/variants/dojo/overridetree.cb b/src/mainboard/google/cherry/variants/dojo/overridetree.cb new file mode 100644 index 0000000000..1dff594736 --- /dev/null +++ b/src/mainboard/google/cherry/variants/dojo/overridetree.cb @@ -0,0 +1,22 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8195 + device domain 0 on + register "pcie_config" = "{ + .base = 0x112f0000, + .mmio_res_io = { + .cpu_addr = 0x20000000, + .pci_addr = 0x20000000, + .size = 16 * MiB, + .type = IORESOURCE_IO, + }, + .mmio_res_mem = { + .cpu_addr = 0x21000000, + .pci_addr = 0x21000000, + .size = 48 * MiB, + .type = IORESOURCE_MEM, + }, + }" + device pci 00.0 on end # - Host Bridge + end +end |