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authorDavid Wu <david_wu@quanta.corp-partner.google.com>2020-08-28 17:02:38 +0800
committerEdward O'Callaghan <quasisec@chromium.org>2020-08-31 05:36:36 +0000
commit1bea841b2f5ba8e700039bb3f048dc0e0ba5e52f (patch)
tree0ac2bf4312402ea18398aa9994e952cc03292a19
parent1c97793b79cb68894d9600fee15fed7bf2d399c8 (diff)
mb/google/puff: Set TCC offset to 5 for kaisa and duffy
Set tcc offset to 5 degree celsius for kaisa and duffy BUG=b:166696500 BRANCH=puff TEST=Build, and verify test result by thermal team. Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/hatch/variants/duffy/overridetree.cb1
-rw-r--r--src/mainboard/google/hatch/variants/kaisa/overridetree.cb1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/duffy/overridetree.cb b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
index 10da16163d..a4fa09d3c2 100644
--- a/src/mainboard/google/hatch/variants/duffy/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/duffy/overridetree.cb
@@ -1,4 +1,5 @@
chip soc/intel/cannonlake
+ register "tcc_offset" = "5" # TCC of 95C
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index dbf1851f32..c6aef059a7 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -1,4 +1,5 @@
chip soc/intel/cannonlake
+ register "tcc_offset" = "5" # TCC of 95C
# Auto-switch between X4 NVMe and X2 NVMe.
register "TetonGlacierMode" = "1"