diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-04-04 09:15:20 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-11 16:23:54 +0000 |
| commit | 1b767725a5cb75d6799c5dadb89337c4d2a5fa49 (patch) | |
| tree | 7f2f2c898d768de1cd9de4d985d905938c67a70b | |
| parent | e84b095d3a238ae5fd734c4c186132a4e07eea07 (diff) | |
mb/siemens/mc_ehl2: Fix GPIO settings for latest HW revision
With the latest hardware revision, the two GPIOs GPD11 and GPP_C8 are no
longer used.
BUG=none
TEST=Checked output verbose GPIO debug messages
Change-Id: Ia06f93aee4eccb0e4230f0c3ef53922d42701f21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74201
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c index 72994bbde8..20a89c64d1 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/gpio.c @@ -72,8 +72,7 @@ static const struct pad_config gpio_table[] = { /* Community 2 - GpioGroup DSW */ PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), /* ACPRESENT */ PAD_NC(GPD9, NONE), /* Not connected */ - /* ONBOARD_X4_PCIE_SLOT1_RESET_N */ - PAD_CFG_GPO(GPD11, 1, PLTRST), + PAD_NC(GPD11, NONE), /* Not connected */ /* Community 3 - GpioGroup GPP_S */ PAD_NC(GPP_S0, NONE), /* Not connected */ @@ -110,6 +109,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE1_MDC */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE1_MDIO */ + PAD_NC(GPP_C8, NONE), /* Not connected */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */ |