intel/i945 gm45: Use acpi_s3_resume_allowed()

Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6061
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>

8 files changed, 88 insertions, 85 deletions

diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index a081a8a8a2..0f746e1b75 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
@@ -304,17 +305,16 @@ void main(unsigned long bist)
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		boot_mode = 2;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+		if (acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			boot_mode = 2;
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		}
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 418b6e430d..2ee45fead9 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include <superio/winbond/common/winbond.h>
 #include <superio/winbond/w83627ehg/w83627ehg.h>
@@ -255,16 +256,16 @@ void main(unsigned long bist)
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		boot_mode = 2;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+		if (acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			boot_mode = 2;
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		}
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 69d4232edd..1ae632debc 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -26,6 +26,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include "superio/smsc/lpc47m15x/lpc47m15x.h"
 #include <pc80/mc146818rtc.h>
@@ -215,16 +216,16 @@ void main(unsigned long bist)
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		boot_mode = 2;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+		if (acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			boot_mode = 2;
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		}
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 4acd734cc7..06a74c420c 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -22,6 +22,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <lib.h>
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
@@ -366,17 +367,16 @@ void main(unsigned long bist)
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		boot_mode = 2;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+		if (acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			boot_mode = 2;
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		}
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index dae917c925..9c7f62486c 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -29,6 +29,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include <timestamp.h>
 #include <pc80/mc146818rtc.h>
@@ -264,17 +265,16 @@ void main(unsigned long bist)
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		boot_mode = 2;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+		if (acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			boot_mode = 2;
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		}
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 1198fb2007..1d9f68b5f2 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -29,6 +29,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include <timestamp.h>
 #include <pc80/mc146818rtc.h>
@@ -266,17 +267,16 @@ void main(unsigned long bist)
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		boot_mode = 2;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+		if (acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			boot_mode = 2;
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		}
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index ad323f5501..e8bbb14f2d 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -28,6 +28,7 @@
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <lib.h>
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
@@ -291,17 +292,16 @@ void main(unsigned long bist)
 	reg32 = inl(DEFAULT_PMBASE + 0x04);
 	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 	if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		boot_mode = 2;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+		if (acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			boot_mode = 2;
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		}
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 90392b9eb5..63d55a3d46 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -27,6 +27,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
+#include <arch/acpi.h>
 #include <cbmem.h>
 #include <lib.h>
 #include <pc80/mc146818rtc.h>
@@ -155,16 +156,16 @@ void main(unsigned long bist)
 	/* Check for S3 resume. */
 	const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
 	if (((pm1_cnt >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
-		s3resume = 1;
-		/* Clear SLP_TYPE. This will break stage2 but
-		 * we care for that when we get there.
-		 */
-		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-#else
-		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+		if (acpi_s3_resume_allowed()) {
+			printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+			s3resume = 1;
+			/* Clear SLP_TYPE. This will break stage2 but
+			 * we care for that when we get there.
+			 */
+			outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+		} else {
+			printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+		}
 	}
 
 	/* RAM initialization */