soc/intel/xeon_sp/cpx: add IIO stack resources to DSDT

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Iec89551a8b88a683db5857e3a6ab4af5e446cb5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

1 files changed, 69 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
index b648262347..4a5cb64269 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/acpi.c
@@ -37,6 +37,72 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	return current;
 }
 
+static void uncore_inject_dsdt(void)
+{
+	struct iiostack_resource stack_info = {0};
+
+	get_iiostack_info(&stack_info);
+
+	acpigen_write_scope("\\_SB");
+
+	for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) {
+		const STACK_RES *ri = &stack_info.res[stack];
+		char rtname[16];
+
+		snprintf(rtname, sizeof(rtname), "RT%02x", stack);
+
+		acpigen_write_name(rtname);
+		printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n",
+			rtname, stack);
+
+		acpigen_write_resourcetemplate_header();
+
+		/* bus resource */
+		acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit,
+			0x0, (ri->BusLimit - ri->BusBase + 1));
+
+		/* additional io resources on socket 0 bus 0 */
+		if (stack == 0) {
+			/* ACPI 6.4.2.5 I/O Port Descriptor */
+			acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
+
+			/* IO decode  CF8-CFF */
+			acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0);
+			acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918);
+			acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C);
+			acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020);
+		}
+
+		/* IO resource */
+		acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
+			ri->PciResourceIoLimit, 0x0,
+			(ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
+
+		/* additional mem32 resources on socket 0 bus 0 */
+		if (stack == 0) {
+			acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS,
+				(VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0,
+				VGA_BASE_SIZE);
+			acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
+				(SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
+				SPI_BASE_SIZE);
+		}
+
+		/* Mem32 resource */
+		acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
+			ri->PciResourceMem32Limit, 0x0,
+			(ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
+
+		/* Mem64 resource */
+		acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base,
+			ri->PciResourceMem64Limit, 0x0,
+			(ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
+
+		acpigen_write_resourcetemplate_footer();
+	}
+	acpigen_pop_len();
+}
+
 void southbridge_inject_dsdt(const struct device *device)
 {
 	global_nvs_t *gnvs;
@@ -59,6 +125,9 @@ void southbridge_inject_dsdt(const struct device *device)
 		acpigen_write_name_dword("NVSA", (uint32_t)gnvs);
 		acpigen_pop_len();
 	}
+
+	/* Add IIOStack ACPI Resource Templates */
+	uncore_inject_dsdt();
 }
 
 void acpi_create_gnvs(struct global_nvs_t *gnvs)