diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-10-05 14:41:15 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-10-12 15:08:21 +0000 |
| commit | 10509c6f190c791d4e06006610dd83200c9fad37 (patch) | |
| tree | d2fa454e07aa2f5689a7c168052647400df24da6 | |
| parent | ba748cc7c0136e031249ddd831cc49f14885dc97 (diff) | |
amd/stoneyridge: Remove hudson register definitions
Delete artifacts remaining from the original "hudson" and "yangtze"
controller hub designs.
Husdon devices had a configurable AcpiMmio base address, and a selection
for I/O vs. MMIO decode. Modern products are fixed at 0xfed80000 in MMIO.
Remove the flash control register definitions for the old generations.
The manual reset register appears to not function as hudson.
PMIO_DEBUG is named differently now, and not used, so remove its
definition too.
Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index a3c4c7ca8d..e7a8cc32ed 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -40,7 +40,6 @@ #define PM_PCI_CTRL 0x08 #define FORCE_SLPSTATE_RETRY BIT(25) #define FORCE_STPCLK_RETRY BIT(24) -#define PM_ACPI_MMIO_EN 0x24 #define PM_SERIRQ_CONF 0x54 #define PM_SERIRQ_NUM_BITS_17 0x0000 #define PM_SERIRQ_NUM_BITS_18 0x0004 @@ -92,10 +91,6 @@ #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN BIT(5) #define PM_RST_STATUS 0xc0 -#define PM_PMIO_DEBUG 0xd2 -#define PM_MANUAL_RESET 0xd3 -#define PM_HUD_SD_FLASH_CTRL 0xe7 -#define PM_YANG_SD_FLASH_CTRL 0xe8 #define PM_PCIB_CFG 0xea #define PM_GENINT_DISABLE BIT(0) #define PM_LPC_GATING 0xec |