diff options
| author | V Sowmya <v.sowmya@intel.com> | 2022-07-05 20:56:55 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-07-08 07:22:25 +0000 |
| commit | 0f7580e5cc252866f710dee402aa43682b73e7b8 (patch) | |
| tree | 6108d3a7dc4f4e7cee2e3559118912dcebacebce | |
| parent | 4be8d9e80debf56f8ee7998dd4f7f22a65384a04 (diff) | |
mb/google/nissa: Disable the Package C-state demotion
Disabling the Package C-state demotion feature for nissa baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=b:235005582
TEST=Boot and verify that S0ix issue is resolved.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I4d586b962c27b86ee75651dcd655bc0868504646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65664
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 8a5c97e46a..6cc2cb0a17 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -81,6 +81,10 @@ chip soc/intel/alderlake register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1" + # FIXME: To be enabled in future based on PNP impact data. + # Disable Package C-state demotion for nissa baseboard. + register "disable_package_c_state_demotion" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |