diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-09-07 16:11:29 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-09 13:47:58 +0000 |
| commit | 0f08d37d20d3a859b4b12f5420b2554db98a1500 (patch) | |
| tree | 0425f0576131046e3e68cfd53e63e6c385acf555 | |
| parent | dfe2ef082f3af7d0e1d369b24b4df98486992853 (diff) | |
mb/prodrive/atlas: Set i225 PCIe RP as built in
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I4436a9d75cb06f2f51979f2bc57d48fa3dbb9e00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67411
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/prodrive/atlas/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index d458dfa83b..42d5b44c37 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -82,7 +82,7 @@ chip soc/intel/alderlake # Enable PCIe-to-i225 bridge using clk 1 register "pch_pcie_rp[PCH_RP(10)]" = "{ .clk_src = 1, - .flags = PCIE_RP_LTR | PCIE_RP_AER, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, .pcie_rp_aspm = ASPM_DISABLE, }" register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" |