soc/intel: Rename heci_init to cse_init

This patch renames heci_init() to cse_init() as HECI initialization
should have a bigger scope than just initializing the CSE
(a.k.a HECI1 alone).

BUG=none
TEST=Able to build and boot google/taeko.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic7edd55ccdcd70b244615fa06f81803a0ae6ce80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>

9 files changed, 15 insertions, 11 deletions

diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index 3f29fc30b9..48d9a6f64d 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -133,7 +133,7 @@ void mainboard_romstage_entry(void)
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
 	/* Initialize HECI interface */
-	heci_init(HECI1_BASE_ADDRESS);
+	cse_init(HECI1_BASE_ADDRESS);
 
 	if (CONFIG(SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE))
 		pre_mem_debug_init();
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 236a122cb4..1ea91da920 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -125,7 +125,7 @@ void mainboard_romstage_entry(void)
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
 	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
+	cse_init(HECI1_BASE_ADDRESS);
 
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index d284a9d638..e01b1cf920 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -85,11 +85,11 @@ static uintptr_t get_cse_bar(pci_devfn_t dev)
 }
 
 /*
- * Initialize the device with provided temporary BAR. If BAR is 0 use a
+ * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a
  * default. This is intended for pre-mem usage only where BARs haven't been
  * assigned yet and devices are not enabled.
  */
-void heci_init(uintptr_t tempbar)
+void cse_init(uintptr_t tempbar)
 {
 	pci_devfn_t dev = PCH_DEV_CSE;
 
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 8fd8ba0e1a..28bc2503be 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -326,8 +326,12 @@ struct cse_boot_perf_rsp {
 	uint32_t timestamp[NUM_CSE_BOOT_PERF_DATA];
 } __packed;
 
-/* set up device for use in early boot enviroument with temp bar */
-void heci_init(uintptr_t bar);
+/*
+ * Initialize the CSE device.
+ *
+ * Set up CSE device for use in early boot environment with temp bar.
+ */
+void cse_init(uintptr_t bar);
 
 /*
  * Send message from BIOS_HOST_ADDR to cse_addr.
diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c
index ecbdd97e04..39a5a332b2 100644
--- a/src/soc/intel/elkhartlake/romstage/romstage.c
+++ b/src/soc/intel/elkhartlake/romstage/romstage.c
@@ -131,7 +131,7 @@ void mainboard_romstage_entry(void)
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
 	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
+	cse_init(HECI1_BASE_ADDRESS);
 
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
index 1dc618c7ee..8575a3f7c0 100644
--- a/src/soc/intel/icelake/romstage/romstage.c
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -114,7 +114,7 @@ void mainboard_romstage_entry(void)
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
 	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
+	cse_init(HECI1_BASE_ADDRESS);
 
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c
index f7e6a91b6e..3a2f8b4e6f 100644
--- a/src/soc/intel/jasperlake/romstage/romstage.c
+++ b/src/soc/intel/jasperlake/romstage/romstage.c
@@ -131,7 +131,7 @@ void mainboard_romstage_entry(void)
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
 	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
+	cse_init(HECI1_BASE_ADDRESS);
 
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 7e891b19f8..30401fc0b9 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -129,7 +129,7 @@ void mainboard_romstage_entry(void)
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
 	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
+	cse_init(HECI1_BASE_ADDRESS);
 	ps = pmc_get_power_state();
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);
diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c
index 872cca5c52..3c6e634f38 100644
--- a/src/soc/intel/tigerlake/romstage/romstage.c
+++ b/src/soc/intel/tigerlake/romstage/romstage.c
@@ -131,7 +131,7 @@ void mainboard_romstage_entry(void)
 	/* Program SMBus base address and enable it */
 	smbus_common_init();
 	/* initialize Heci interface */
-	heci_init(HECI1_BASE_ADDRESS);
+	cse_init(HECI1_BASE_ADDRESS);
 
 	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
 	fsp_memory_init(s3wake);