diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-05-15 04:32:08 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-06-28 11:27:34 +0000 |
| commit | 0a6f5188e80d888529e2067d02add19f65cb013c (patch) | |
| tree | 05b052963e295911fa67fc0b41169d0393317fb2 | |
| parent | bcd247376633b0fb4f1dbfbf8c2e02d2c926adec (diff) | |
soc/intel/xeon_sp: Reserve MMIO range for VTd BAR dynamically
vtd_probe_bar_size is used to decide the BAR size.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ie45dd29e386cbfcb136ce2152aba2ec67757ee3c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82431
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/chip_common.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/uncore.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/uncore_acpi.c | 7 |
3 files changed, 22 insertions, 4 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 5fd5dc6f18..3f4c77e15f 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -90,4 +90,6 @@ bool is_cxl_domain(const struct device *dev); void unlock_pam_regions(void); +size_t vtd_probe_bar_size(struct device *dev); + #endif /* _CHIP_COMMON_H_ */ diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index d2d46220a2..96451913fd 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -51,6 +51,20 @@ enum { NUM_MAP_ENTRIES }; +size_t vtd_probe_bar_size(struct device *dev) +{ + uint32_t id = pci_read_config32(dev, PCI_VENDOR_ID); + assert(id == (PCI_VID_INTEL | (MMAP_VTD_CFG_REG_DEVID << 16))); + + uint32_t val = pci_read_config32(dev, VTD_BAR_CSR); + pci_write_config32(dev, VTD_BAR_CSR, (uint32_t)(-4 * KiB)); + size_t size = (~(pci_read_config32(dev, VTD_BAR_CSR) & ((uint32_t)(-4 * KiB)))) + 1; + assert(size != 0); + pci_write_config32(dev, VTD_BAR_CSR, val); + + return size; +} + static struct map_entry memory_map[NUM_MAP_ENTRIES] = { [TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"), [MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"), @@ -211,7 +225,8 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) mc_report_map_entries(dev, &mc_values[0]); if (mc_values[VTDBAR_REG]) { - res = mmio_range(dev, VTD_BAR_CSR, mc_values[VTDBAR_REG], 8 * KiB); + res = mmio_range(dev, VTD_BAR_CSR, mc_values[VTDBAR_REG], + vtd_probe_bar_size(dev)); LOG_RESOURCE("vtd_bar", dev, res); } diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index a0bbbff9e1..22f8b6fed0 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -272,12 +272,13 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd_4k(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base, vtd_probe_bar_size(iommu)); } else { printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); - current += acpi_create_dmar_drhd_4k(current, 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base, + vtd_probe_bar_size(iommu)); } // Add PCH IOAPIC |