soc/intel/alderlake: Support PCIe hardware compliance test mode

The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...

This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag

BUG=b:235863379
TEST=Compilation with and without the flag
     Verify code path with instrumentation

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic07b9276121dfbd273a8f63a1f775ddbd3566884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

3 files changed, 11 insertions, 2 deletions

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index c973d3bf47..4406b3e65a 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -118,6 +118,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_INTEL_CSE_SET_EOP
 	select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY if SOC_INTEL_CSE_LITE_SKU
 	select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
+	select HAVE_INTEL_COMPLIANCE_TEST_MODE
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index cbc7471115..19040d8651 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -864,7 +864,8 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 				get_l1_substate_control(rp_cfg->PcieRpL1Substates);
 		s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
 		s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
-		s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
+		s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
+				|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
 		if (rp_cfg->pcie_rp_aspm)
 			s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm);
@@ -873,6 +874,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
 			s_cfg->PcieRpSlotImplemented[i] = 0;
 		s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms;
 	}
+	s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 }
 
 static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg,
@@ -891,9 +893,11 @@ static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg,
 			get_l1_substate_control(rp_cfg->PcieRpL1Substates);
 		s_cfg->CpuPcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
 		s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
-		s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
+		s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG)
+				|| CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 		s_cfg->PtmEnabled[i] = 0;
 	}
+	s_cfg->CpuPcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE);
 }
 
 static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index f8bdb41f2a..4e58c29008 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -54,6 +54,10 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
 	static unsigned int clk_req_mapping = 0;
 
 	for (i = 0; i < cfg_count; i++) {
+		if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) {
+			m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
+			continue;
+		}
 		if (!(en_mask & BIT(i)))
 			continue;
 		if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)