mb/siemens/mc_apl: Correct multi-line comment style for all Siemens APL Boards

Change-Id: I6578aee52e6900b25441dc119383856acc480231
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

14 files changed, 153 insertions, 231 deletions

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
index 6a3b859f55..5cfacb8291 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c
@@ -3,11 +3,9 @@
 #include <commonlib/helpers.h>
 #include <baseboard/variants.h>
 
-/*
- * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
- * table found in EDS vol 1, but some pins aren't grouped functionally in
- * the table so those were moved for more logical grouping.
- */
+/* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' table found in
+   EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
+   more logical grouping. */
 static const struct pad_config gpio_table[] = {
 
 	/* Southwest Community */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c
index bad4da79ea..901899f6ed 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c
@@ -61,8 +61,8 @@ enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg)
 		return CB_ERR;
 	}
 
-	/* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters: */
-	/* Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */
+	/* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters:
+	   Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */
 	cfg->dp_interface_ctrl = 0x00;
 	/* Use even bus for LVDS clock distribution only. */
 	cfg->lvds_interface_ctrl1 = 0x00;
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
index c94bfb835b..78723c2a19 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c
@@ -3,11 +3,9 @@
 #include <commonlib/helpers.h>
 #include <baseboard/variants.h>
 
-/*
- * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
- * table found in EDS vol 1, but some pins aren't grouped functionally in
- * the table so those were moved for more logical grouping.
- */
+/* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' table found in
+   EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
+   more logical grouping. */
 static const struct pad_config gpio_table[] = {
 
 	/* Southwest Community */
@@ -159,22 +157,18 @@ static const struct pad_config gpio_table[] = {
 
 	/* Northwest Community */
 
-	/* DDI0_DDC_DATA_1V8 - I2C Data for HDMI - Connected to a MUX SEL IC to
-	 * choose between DDI0_AUXP (Port 0: Display Port Auxiliary Channel for
-	 * DP/HDMI) controlled by resistor stuffing options.
-	 */
+	/* DDI0_DDC_DATA_1V8 - I2C Data for HDMI - Connected to a MUX SEL IC to choose between
+	   DDI0_AUXP (Port 0: Display Port Auxiliary Channel for DP/HDMI) controlled by
+	   resistor stuffing options. */
 	PAD_CFG_NF(GPIO_187, UP_20K, DEEP, NF1),
-	/* DDI0_DDC_CLK_1V8  - I2C Clock for HDMI - Connected to a MUX SEL IC
-	 * to choose between DDI0_AUXN controlled by resistor stuffing options.
-	 */
+	/* DDI0_DDC_CLK_1V8  - I2C Clock for HDMI - Connected to a MUX SEL IC to choose between
+	   DDI0_AUXN controlled by resistor stuffing options. */
 	PAD_CFG_NF(GPIO_188, UP_20K, DEEP, NF1),
-	/* DDI1_DDC_DATA_1V8 - I2C Data for HDMI - Connected to a MUX SEL IC to
-	 * choose between DDI1_AUXN.
-	 */
+	/* DDI1_DDC_DATA_1V8 - I2C Data for HDMI - Connected to a MUX SEL IC to choose between
+	   DDI1_AUXN. */
 	PAD_CFG_NF(GPIO_189, UP_20K, DEEP, NF1),
-	/* DDI1_DDC_CLK_1V8  - I2C Clock for HDMI - Connected to a MUX SEL IC
-	 * to choose between DDI1_AUXP.
-	 */
+	/* DDI1_DDC_CLK_1V8  - I2C Clock for HDMI - Connected to a MUX SEL IC to choose between
+	   DDI1_AUXP. */
 	PAD_CFG_NF(GPIO_190, UP_20K, DEEP, NF1),
 
 	/* Not connected */
@@ -184,39 +178,27 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME),
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME),
 
-	/* EDP_VDD_EN_1V8  (DNI) - Alternative stuffing option for
-	 * PTN3460 LVDS_VDD_EN.
-	 */
+	/* EDP_VDD_EN_1V8  (DNI) - Alternative stuffing option for PTN3460 LVDS_VDD_EN. */
 	PAD_CFG_TERM_GPO(GPIO_196, 1, UP_20K, DEEP),
-	/* EDP_BKLT_EN_1V8 (DNI) - Alternative stuffing option for
-	 * PTN3460 LVDS_BKLT_EN
-	 */
+	/* EDP_BKLT_EN_1V8 (DNI) - Alternative stuffing option for PTN3460 LVDS_BKLT_EN */
 	PAD_CFG_TERM_GPO(GPIO_197, 1, UP_20K, DEEP),
-	/* EDP_BKLT_CTRL_1V8 - Alternative stuffing option for
-	 * PTN3460 LVDS_BKLT_CTRL
-	 */
+	/* EDP_BKLT_CTRL_1V8 - Alternative stuffing option for PTN3460 LVDS_BKLT_CTRL */
 	PAD_CFG_TERM_GPO(GPIO_198, 1, UP_20K, DEEP),
 
-	/* DDI1_HPD# - Connect to DP1_HPD Hot plug detection signal of SMARC
-	 * Connector.
-	 */
+	/* DDI1_HPD# - Connect to DP1_HPD Hot plug detection signal of SMARC Connector. */
 	PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2),
-	/* DDI0_HPD# - Connect to DP0_HPD Hot plug detection signal of SMARC
-	 * Connector.
-	 */
+	/* DDI0_HPD# - Connect to DP0_HPD Hot plug detection signal of SMARC Connector. */
 	PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2),
 
 	/* Not connected */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME),
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, DN_20K, DEEP, NF1, Tx0RxDCRx0, SAME),
 
-	/* USB2_OC0_1V8# - Connected to (USB0_OC#:MUX_SEL[USB2_OTG_0/USB2_6]),
-	 * (USB1_OC#:USB1), (USB2_OC#:USB2)
-	 */
+	/* USB2_OC0_1V8# - Connected to (USB0_OC#:MUX_SEL[USB2_OTG_0/USB2_6]), (USB1_OC#:USB1),
+	   (USB2_OC#:USB2) */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, MASK, SAME),
-	/* USB2_OC1_1V8# - Connected to (USB3_OC#:USB3), (USB4_OC#:USB4),
-	 * (USB5_OC#:USB5). NOTE: USB2_7_WIBU do not have OC.
-	 */
+	/* USB2_OC1_1V8# - Connected to (USB3_OC#:USB3), (USB4_OC#:USB4), (USB5_OC#:USB5).
+	   NOTE: USB2_7_WIBU do not have OC. */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, MASK, SAME),
 
 	/* Not connected */
@@ -245,23 +227,17 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_INT(PMIC_I2C_SCL, DN_20K, DEEP, OFF),
 	PAD_CFG_GPI_INT(PMIC_I2C_SDA, DN_20K, DEEP, OFF),
 
-	/* I2S_MCLK - Connected to SMARC Connector I2S0_CLK  - Digital audio
-	 * clock
-	 */
+	/* I2S_MCLK - Connected to SMARC Connector I2S0_CLK  - Digital audio clock */
 	PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1),
-	/* I2S_BCLK - Connected to SMARC Connector I2S0_LRCK - Left & Right
-	 * audio synchronization clock
-	 */
+	/* I2S_BCLK - Connected to SMARC Connector I2S0_LRCK - Left & Right audio
+	   synchronization clock */
 	PAD_CFG_NF(GPIO_75, DN_20K, DEEP, NF1),
 	/* Not connected */
 	PAD_CFG_GPI_INT(GPIO_76, DN_20K, DEEP, OFF),
-	/* I2S_SDI - Connected to SMARC Connector I2S0_SDI - Digital audio
-	 * Input
-	 */
+	/* I2S_SDI - Connected to SMARC Connector I2S0_SDI - Digital audio Input */
 	PAD_CFG_NF(GPIO_77, DN_20K, DEEP, NF1),
-	/* I2S_SD0 & STRAP_GPIO_78 (int. PU)  - Connected to SMARC Connector
-	 * I2S0_SDO - Digital audio Output
-	 */
+	/* I2S_SD0 & STRAP_GPIO_78 (int. PU)  - Connected to SMARC Connector I2S0_SDO - Digital
+	   audio Output */
 	PAD_CFG_NF(GPIO_78, DN_20K, DEEP, NF1),
 
 	/* Not connected */
@@ -273,9 +249,8 @@ static const struct pad_config gpio_table[] = {
 	/* Not connected */
 	PAD_CFG_GPI_INT(GPIO_83, DN_20K, DEEP, OFF),
 
-	/* HDA_RST_1V8# - MUX SEL with CPLD pin and then goto GPIO4/HDA_RST#
-	 * pin of SMARC connector
-	 */
+	/* HDA_RST_1V8# - MUX SEL with CPLD pin and then goto GPIO4/HDA_RST# pin of SMARC
+	   connector */
 	PAD_CFG_NF(GPIO_84, UP_20K, DEEP, NF2),
 	/* Not connected */
 	PAD_CFG_GPI_INT(GPIO_85, DN_20K, DEEP, OFF),
@@ -291,14 +266,12 @@ static const struct pad_config gpio_table[] = {
 	/* STRAP_GPIO_92 (int. PD) */
 	PAD_CFG_GPI_INT(GPIO_92, DN_20K, DEEP, OFF),
 
-	/* CS0 for BIOS SPI. Connected to CPLD. CPLD then MUX SEL to either SPI
-	 * FLASH CHIP on module (SPI_CS_MODULE_1V8#) or to the carrier board
-	 * SPI FLASH Chip (SPI_CS_EXT_1V8#).
-	 */
+	/* CS0 for BIOS SPI. Connected to CPLD. CPLD then MUX SEL to either SPI FLASH CHIP on
+	   module (SPI_CS_MODULE_1V8#) or to the carrier board SPI FLASH Chip
+	   (SPI_CS_EXT_1V8#). */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_97, NATIVE, DEEP, NF1, MASK, SAME),
-	/* CS1 for BIOS SPI. Connected to CPLD. Not used, because we use 1x16MB
-	 * Flash and not 2x8MB Flash.
-	 */
+	/* CS1 for BIOS SPI. Connected to CPLD. Not used, because we use 1x16MB Flash and not
+	   2x8MB Flash. */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NATIVE, DEEP, NF1, MASK, SAME),
 	/* FST_SPI_MISO_1V8 */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NATIVE, DEEP, NF1, MASK, SAME),
@@ -355,30 +328,23 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, DN_20K, DEEP, NF1, HIZCRx0, SAME),
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF1, HIZCRx0, SAME),
 
-	/* OTG_SEL_1V8 - Connected to a USB MUX to select between USB2_DP0 (OTG)
-	 * and USB2_DP6. 1:OTG, 0:USB
-	 */
+	/* OTG_SEL_1V8 - Connected to a USB MUX to select between USB2_DP0 (OTG) and USB2_DP6.
+	   1:OTG, 0:USB */
 	PAD_CFG_TERM_GPO(GPIO_9, 1, UP_20K, DEEP),
-	/* EN_I2CPM_EXT_1V8 - Connected to OE pin of I2C Re-driver.
-	 * Allow/Disallow I2C signal to pass through to SMARC Connector.
-	 */
+	/* EN_I2CPM_EXT_1V8 - Connected to OE pin of I2C Re-driver. Allow/Disallow I2C signal
+	   to pass through to SMARC Connector. */
 	PAD_CFG_TERM_GPO(GPIO_10, 1, UP_20K, DEEP),
-	/* EN_SMB_EXT_1V8 - Connected to OE pin of I2C Re-driver.
-	 * Allow/Disallow SMBUS signal to pass through to SMARC Connector.
-	 */
+	/* EN_SMB_EXT_1V8 - Connected to OE pin of I2C Re-driver. Allow/Disallow SMBUS signal
+	   to pass through to SMARC Connector. */
 	PAD_CFG_TERM_GPO(GPIO_11, 0, UP_20K, DEEP),
-	/* BOOT_SEL2_1V8# - Three Module pins allow the Carrier board user to
-	 * select from eight possible boot devices.
-	 */
+	/* BOOT_SEL2_1V8# - Three Module pins allow the Carrier board user to select from eight
+	   possible boot devices. */
 	PAD_CFG_GPI_INT(GPIO_12, UP_20K, DEEP, OFF),
-	/* BOOT_SEL1_1V8# - BOOT_SEL pins shall be weakly pulled up on the
-	 * Module and the pin states decoded by Module logic.
-	 */
+	/* BOOT_SEL1_1V8# - BOOT_SEL pins shall be weakly pulled up on the Module and the pin
+	   states decoded by Module logic. */
 	PAD_CFG_GPI_INT(GPIO_13, UP_20K, DEEP, OFF),
-	/* BOOT_SEL0_1V8# - For details refer to
-	 * SMARC_Hardware_Specification_V200.pdf page 38 chapter 4.17 Boot
-	 * Select
-	 */
+	/* BOOT_SEL0_1V8# - For details refer to SMARC_Hardware_Specification_V200.pdf page 38
+	   chapter 4.17 Boot Select */
 	PAD_CFG_GPI_INT(GPIO_14, UP_20K, DEEP, OFF),
 	/* GPIO_CPLD_TCK_1V8 */
 	PAD_CFG_TERM_GPO(GPIO_15, 0, DN_20K, DEEP),
@@ -388,43 +354,38 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI_INT(GPIO_17, DN_20K, DEEP, OFF),
 	/* GPIO_CPLD_TDO_1V8 */
 	PAD_CFG_TERM_GPO(GPIO_18, 0, DN_20K, DEEP),
-	/* PM_TEST_1V8# connect to the SMARC Connector TEST# pin.
-	 * Held low by Carrier to invoke Module vendor specific test function.
-	 * Pulled up on Module. Driven by OD part on Carrier.
-	 */
+	/* PM_TEST_1V8# connect to the SMARC Connector TEST# pin. Held low by Carrier to invoke
+	   Module vendor specific test function. Pulled up on Module. Driven by OD part on
+	   Carrier. */
 	PAD_CFG_GPI_INT(GPIO_19, UP_20K, DEEP, OFF),
 	/* MCERR_1V8 - ICT Test Point */
 	PAD_CFG_GPI_INT(GPIO_20, DN_20K, DEEP, OFF),
 	/* IERR_1V8 - ICT Test Point */
 	PAD_CFG_GPI_INT(GPIO_21, DN_20K, DEEP, OFF),
-	/* SLEEP_CPU_1V8# - Connect to the SMARC Connector SLEEP# pin.
-	 * Sleep indicator from Carrier board. May be sourced from user Sleep
-	 * button or Carrier logic. Carrier to float the line in in-active
-	 * state. Active low, level sensitive. Should be de-bounced on the
-	 * Module. Pulled up on Module. Driven by Open Drain (OD) part on
-	 * Carrier.
+	/*
+	 * SLEEP_CPU_1V8# - Connect to the SMARC Connector SLEEP# pin.
+	 * Sleep indicator from Carrier board. May be sourced from user Sleep button or Carrier
+	 * logic. Carrier to float the line in in-active state. Active low, level sensitive.
+	 * Should be de-bounced on the Module. Pulled up on Module. Driven by Open Drain (OD)
+	 * part on Carrier.
 	 */
 	PAD_CFG_GPI_SCI_IOS(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME),
-	/* LID_CPU_1V8# - Connect to the SMARC Connector LID# pin.
-	 * Lid open/close indication to Module. Low indicates lid closure
-	 * (which system may use to initiate a sleep state). Carrier to float
-	 * the line in in-active state. Active low, level sensitive. Should be
-	 * de-bounced on the Module Pulled up on Module. Driven by OD part on
-	 * Carrier.
+	/*
+	 * LID_CPU_1V8# - Connect to the SMARC Connector LID# pin.
+	 * Lid open/close indication to Module. Low indicates lid closure (which system may use
+	 * to initiate a sleep state). Carrier to float the line in in-active state. Active
+	 * low, level sensitive. Should be de-bounced on the Module Pulled up on Module. Driven
+	 * by OD part on Carrier.
 	 */
 	PAD_CFG_GPI_SCI_IOS(GPIO_23, UP_20K, DEEP, EDGE_BOTH, INVERT, TxDRxE, SAME),
-	/* WDT_IRQ1_1V8# (NMI) - Trigger by CPLD Watchdog module when enabled
-	 * and timeout.
-	 */
+	/* WDT_IRQ1_1V8# (NMI) - Trigger by CPLD Watchdog module when enabled and timeout. */
 	PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT),
-	/* WDT_IRQ0_1V8# (SCI) - Refer to Kontron_CPLD.pdf Chapter 6 Watchdog
-	 * Module Description, for how to use it.
-	 */
+	/* WDT_IRQ0_1V8# (SCI) - Refer to Kontron_CPLD.pdf Chapter 6 Watchdog Module
+	   Description, for how to use it. */
 	PAD_CFG_GPI_SCI(GPIO_25, UP_20K, DEEP, LEVEL, INVERT),
 	/* SATA_LED# - Connect to the SMARC Connector SATA_ACT# pin.
-	 * Active low SATA activity indicator. If implemented, shall be able to
-	 * sink 24mA or more Carrier LED current.
-	 */
+	   Active low SATA activity indicator. If implemented, shall be able to sink 24mA or
+	   more Carrier LED current. */
 	PAD_CFG_NF(GPIO_26, DN_20K, DEEP, NF5),
 
 	/* SMB_ALERT_GPIO# */
@@ -452,9 +413,8 @@ static const struct pad_config gpio_table[] = {
 	/* Not connected */
 	PAD_CFG_TERM_GPO(GPIO_37, 0, DN_20K, DEEP),
 
-	/* GPIO_VALID (CPLD=gpio_valid/pi_gpio_en)- This pin Enable the CPLD
-	 * GPIO to the SMARC Connector.
-	 */
+	/* GPIO_VALID (CPLD=gpio_valid/pi_gpio_en)- This pin Enable the CPLD GPIO to the SMARC
+	   Connector. */
 	PAD_CFG_TERM_GPO(GPIO_62, 1, UP_20K, DEEP),
 	/* LVDS_ENABLE_1V8# connect to PTN3460 DP to LVDS converter chip. */
 	PAD_CFG_TERM_GPO(GPIO_63, 0, DN_20K, DEEP),
@@ -462,8 +422,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_64, DN_20K, DEEP, HIZCRx0, SAME),
 	/* Not connected */
 	PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_65, DN_20K, DEEP, HIZCRx0, SAME),
-	/* CAM_CS0_CS1_SEL - Serial Cameras interfaces Select - to select
-	 * between the two MIPI CSI camera interfaces on the SMARC connector. */
+	/* CAM_CS0_CS1_SEL - Serial Cameras interfaces Select - to select between the two MIPI
+	   CSI camera interfaces on the SMARC connector. */
 	PAD_CFG_TERM_GPO(GPIO_66, 0, DN_20K, DEEP),
 	/* MCSI0_RST_1V8# - Reset the MIPI CSI camera interfaces 0 */
 	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, HIZCRx0, SAME),
@@ -502,10 +462,8 @@ static const struct pad_config gpio_table[] = {
 	/* Not connected */
 	PAD_CFG_GPIO_DRIVER_HI_Z(CNV_BRI_DT, DN_20K, DEEP, MASK, SAME),
 	/* PM_FORCE_RECOV_1V8# from SMARC Connector FORCE_RECOV#.
-	 * A low on the Module FORCE_RECOV# pin may invoke the SOC native Force
-	 * Recovery mode.
-	 * For x86 systems this signal may be used to load BIOS defaults.
-	 */
+	   A low on the Module FORCE_RECOV# pin may invoke the SOC native Force Recovery mode.
+	   For x86 systems this signal may be used to load BIOS defaults. */
 	PAD_CFG_GPIO_DRIVER_HI_Z(CNV_BRI_RSP, UP_20K, DEEP, MASK, SAME),
 	/* Not connected */
 	PAD_CFG_GPIO_DRIVER_HI_Z(CNV_RGI_DT, DN_20K, DEEP, MASK, SAME),
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
index 8ab0a93f14..e7b9bd0e3a 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
@@ -3,11 +3,9 @@
 #include <commonlib/helpers.h>
 #include <baseboard/variants.h>
 
-/*
- * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
- * table found in EDS vol 1, but some pins aren't grouped functionally in
- * the table so those were moved for more logical grouping.
- */
+/* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' table found in
+   EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
+   more logical grouping. */
 static const struct pad_config gpio_table[] = {
 
 	/* Southwest Community */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
index bf87109add..c17f1be411 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
@@ -21,18 +21,17 @@ void variant_mainboard_final(void)
 	struct device *dev = NULL;
 
 	/* PIR6 register mapping for PCIe root ports
-	 * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC#
-	 */
+	   INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# */
 	pcr_write16(PID_ITSS, 0x314c, 0x2103);
 
 	/* Enable CLKRUN_EN for power gating LPC */
 	lpc_enable_pci_clk_cntl();
 
 	/*
-	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
-	 * offset 0x341D bit3 and bit0.
-	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
-	 * offset 0x341C bit [3:0].
+	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 offset 0x341D
+	 * bit3 and bit0.
+	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 offset 0x341C bit
+	 * [3:0].
 	 */
 	pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
 
@@ -42,17 +41,15 @@ void variant_mainboard_final(void)
 		if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
 			pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
-		/* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream
-		 * XIO2001 PCIe to PCI Bridge.
-		 */
+		/* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream XIO2001 PCIe to PCI
+		   Bridge. */
 		struct device *parent = dev->bus->dev;
 		if (parent && parent->device == PCI_DID_TI_XIO2001)
 			pci_write_config8(parent, 0xd8, 0x1d);
 	}
 
-	/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI
-	 * Bridge on this mainboard.
-	 */
+	/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI Bridge on this
+	   mainboard. */
 	dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
 	if (dev) {
 		struct device *parent = dev->bus->dev;
@@ -60,11 +57,9 @@ void variant_mainboard_final(void)
 			pci_write_config8(parent, 0xd8, 0x3c);
 	}
 
-	/* Set Full Reset Bit in Reset Control Register (I/O port CF9h).
-	 * When Bit 3 is set to 1 and then the reset button is pressed the PCH
-	 * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard
-	 * to generate the right reset timing.
-	 */
+	/* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1
+	   and then the reset button is pressed the PCH will drive SLP_S3 active (low). SLP_S3
+	   is then used on the mainboard to generate the right reset timing. */
 	outb(FULL_RST, RST_CNT);
 }
 
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c
index 32bc61bf05..369e1f8dae 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c
@@ -3,11 +3,9 @@
 #include <commonlib/helpers.h>
 #include <baseboard/variants.h>
 
-/*
- * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
- * table found in EDS vol 1, but some pins aren't grouped functionally in
- * the table so those were moved for more logical grouping.
- */
+/* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' table found in
+   EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
+   more logical grouping. */
 static const struct pad_config gpio_table[] = {
 	/* Southwest Community */
 
@@ -46,11 +44,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1),	/* SDCARD_D3 */
 	PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1),	/* SDCARD_CD_N */
 	PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1),	/* SDCARD_CMD */
-	/*
-	 * SDCARD_CLK_FB - APL EDS Vol1 remarks:
-	 * This is not a physical GPIO that can be used. This Signal is not Ball
-	 * out on the SoC, only the buffer exists.
-	*/
+	/* SDCARD_CLK_FB - APL EDS Vol1 remarks:
+	   This is not a physical GPIO that can be used. This Signal is not Ball out on the
+	   SoC, only the buffer exists. */
 	PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1),
 	PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1),	/* SDCARD_WP_1V8 */
 	PAD_CFG_TERM_GPO(GPIO_183, 1, UP_20K, DEEP),	/* SD_PWR_EN_1V8 */
@@ -71,11 +67,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPIO_132, NONE, DEEP, NF1),	/* provided LPSS_I2C4_SDA */
 	PAD_CFG_NF(GPIO_133, NONE, DEEP, NF1),	/* provided LPSS_I2C4_SCL */
 
-	/*
-	 * Hint for USB enable power: some GPIOs are open drain outputs,
-	 * to drive high -> Bit GPIO_TX_DIS has to be set in combination with PU
-	 * PAD_CFG_GPO macro does not work. Refer to APL EDS Vol 4.
-	 */
+	/* Hint for USB enable power: some GPIOs are open drain outputs, to drive high -> Bit
+	   GPIO_TX_DIS has to be set in combination with PU PAD_CFG_GPO macro does not work.
+	   Refer to APL EDS Vol 4. */
 	PAD_CFG_GPI(GPIO_134, UP_20K, DEEP),		/* enable USB0 power */
 	PAD_CFG_GPI(GPIO_135, UP_20K, DEEP),		/* unused */
 	PAD_CFG_GPI(GPIO_136, UP_20K, DEEP),		/* enable USB7 power */
@@ -210,8 +204,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1),/* FST_IO2 - MEM_CONFIG0 */
 	PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1),/* FST_IO3 - MEM_CONFIG1 */
 	PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1),/* FST_SPI_CLK */
-	/* FST_SPI_CLK_FB - Pad not bonded, default register value is the same
-	 * as here. Refer to Intel Doc APL EDS Vol 1 */
+	/* FST_SPI_CLK_FB - Pad not bonded, default register value is the same as here. Refer
+	   to Intel Doc APL EDS Vol 1 */
 	PAD_CFG_NF(FST_SPI_CLK_FB, NONE, DEEP, NF1),
 
 	/* SIO_SPI_0 for F-module on mainboard */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c
index 7f4334eb9e..26fc27a601 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c
@@ -61,8 +61,8 @@ enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg)
 		return CB_ERR;
 	}
 
-	/* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters: */
-	/* Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */
+	/* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters:
+	   Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */
 	cfg->dp_interface_ctrl = 0x00;
 	/* Use odd bus for LVDS clock distribution only. */
 	cfg->lvds_interface_ctrl1 = 0x01;
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
index 17958a708f..593b2cd1cc 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c
@@ -3,11 +3,9 @@
 #include <commonlib/helpers.h>
 #include <baseboard/variants.h>
 
-/*
- * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
- * table found in EDS vol 1, but some pins aren't grouped functionally in
- * the table so those were moved for more logical grouping.
- */
+/* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' table found in
+   EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
+   more logical grouping. */
 static const struct pad_config gpio_table[] = {
 
 	/* Southwest Community */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c
index 320fcc7f47..c5be046bbe 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c
@@ -16,8 +16,8 @@ static void igd_disable(void)
 
 	/* GMCH Graphics Control Register */
 	ggc = pci_read_config16(root_dev, 0x50);
-	/* Set size of Graphics Translation Table Memory (GGMS) [7:6]
-	 * to 0 and select 0 MB for Graphics Memory (GMS) [15:8]. */
+	/* Set size of Graphics Translation Table Memory (GGMS) [7:6] to 0 and select 0 MB for
+	   Graphics Memory (GMS) [15:8]. */
 	ggc &= ~(0xffc0);
 	/* Disable IGD VGA (IVD). */
 	ggc |= 0x2;
@@ -86,8 +86,8 @@ enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg)
 		return CB_ERR;
 	}
 
-	/* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters: */
-	/* Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */
+	/* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters:
+	   Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */
 	cfg->dp_interface_ctrl = 0x00;
 	/* Use odd bus for LVDS clock distribution only. */
 	cfg->lvds_interface_ctrl1 = 0x01;
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
index 82b8c5bf0f..d01d547096 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
@@ -18,29 +18,24 @@ void variant_mainboard_final(void)
 {
 	struct device *dev = NULL;
 
-	/*
-	 * PIR6 register mapping for PCIe root ports
-	 * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
-	 */
+	/* PIR6 register mapping for PCIe root ports
+	   INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# */
 	pcr_write16(PID_ITSS, 0x314c, 0x0321);
 
 	/* Enable CLKRUN_EN for power gating LPC */
 	lpc_enable_pci_clk_cntl();
 
 	/*
-	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
-	 * offset 0x341D bit3 and bit0.
-	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
-	 * offset 0x341C bit [3:0].
+	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 offset 0x341D
+	 * bit3 and bit0.
+	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 offset 0x341C bit
+	 * [3:0].
 	 */
 	pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
 
-	/*
-	 * Correct the SATA transmit signal via the High Speed I/O Transmit
-	 * Control Register 3.
-	 * Bit [23:16] set the output voltage swing for TX line.
-	 * The value 0x4a sets the swing level to 0.58 V.
-	 */
+	/* Correct the SATA transmit signal via the High Speed I/O Transmit Control Register 3.
+	   Bit [23:16] set the output voltage swing for TX line. The value 0x4a sets the swing
+	   level to 0.58 V. */
 	pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16));
 
 	/* Set Master Enable for on-board PCI device if allowed. */
@@ -49,16 +44,15 @@ void variant_mainboard_final(void)
 		if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
 			pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
-		/* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe
-		 * to PCI Bridge. */
+		/* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI
+		   Bridge. */
 		struct device *parent = dev->bus->dev;
 		if (parent && parent->device == PCI_DID_TI_XIO2001)
 			pci_write_config8(parent, 0xd8, 0x0f);
 	}
 
-	/* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI
-	 * Bridge on this mainboard.
-	 */
+	/* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI Bridge on this
+	   mainboard. */
 	dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
 	if (dev) {
 		struct device *parent = dev->bus->dev;
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
index 8b056cb303..5de6973727 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c
@@ -3,11 +3,9 @@
 #include <commonlib/helpers.h>
 #include <baseboard/variants.h>
 
-/*
- * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
- * table found in EDS vol 1, but some pins aren't grouped functionally in
- * the table so those were moved for more logical grouping.
- */
+/* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' table found in
+   EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
+   more logical grouping. */
 static const struct pad_config gpio_table[] = {
 
 	/* Southwest Community */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
index e730e202c7..b5aa068d34 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
@@ -21,18 +21,17 @@ void variant_mainboard_final(void)
 	struct device *dev = NULL;
 
 	/* PIR6 register mapping for PCIe root ports
-	 * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC#
-	 */
+	   INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# */
 	pcr_write16(PID_ITSS, 0x314c, 0x2103);
 
 	/* Enable CLKRUN_EN for power gating LPC */
 	lpc_enable_pci_clk_cntl();
 
 	/*
-	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2
-	 * offset 0x341D bit3 and bit0.
-	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2
-	 * offset 0x341C bit [3:0].
+	 * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 offset 0x341D
+	 * bit3 and bit0.
+	 * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 offset 0x341C bit
+	 * [3:0].
 	 */
 	pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN));
 
@@ -42,17 +41,15 @@ void variant_mainboard_final(void)
 		if (CONFIG(PCI_ALLOW_BUS_MASTER_ANY_DEVICE))
 			pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 
-		/* Disable clock outputs 0-3 (CLKOUT) for upstream
-		 * XIO2001 PCIe to PCI Bridge.
-		 */
+		/* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe to PCI
+		   Bridge. */
 		struct device *parent = dev->bus->dev;
 		if (parent && parent->device == PCI_DID_TI_XIO2001)
 			pci_write_config8(parent, 0xd8, 0x0F);
 	}
 
-	/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI
-	 * Bridge on this mainboard.
-	 */
+	/* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI Bridge on this
+	   mainboard. */
 	dev = dev_find_device(PCI_VID_SIEMENS, 0x403f, 0);
 	if (dev) {
 		struct device *parent = dev->bus->dev;
@@ -60,11 +57,9 @@ void variant_mainboard_final(void)
 			pci_write_config8(parent, 0xd8, 0x3c);
 	}
 
-	/* Set Full Reset Bit in Reset Control Register (I/O port CF9h).
-	 * When Bit 3 is set to 1 and then the reset button is pressed the PCH
-	 * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard
-	 * to generate the right reset timing.
-	 */
+	/* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1
+	   and then the reset button is pressed the PCH will drive SLP_S3 active (low). SLP_S3
+	   is then used on the mainboard to generate the right reset timing. */
 	outb(FULL_RST, RST_CNT);
 }
 
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/gpio.c
index 2d7bea4341..fb4fe44542 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/gpio.c
@@ -3,11 +3,9 @@
 #include <commonlib/helpers.h>
 #include <baseboard/variants.h>
 
-/*
- * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
- * table found in EDS vol 1, but some pins aren't grouped functionally in
- * the table so those were moved for more logical grouping.
- */
+/* Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' table found in
+   EDS vol 1, but some pins aren't grouped functionally in the table so those were moved for
+   more logical grouping. */
 static const struct pad_config gpio_table[] = {
 	/* Southwest Community */
 
@@ -46,11 +44,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1),	/* SDCARD_D3 */
 	PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1),	/* SDCARD_CD_N */
 	PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1),	/* SDCARD_CMD */
-	/*
-	 * SDCARD_CLK_FB - APL EDS Vol1 remarks:
-	 * This is not a physical GPIO that can be used. This Signal is not Ball
-	 * out on the SoC, only the buffer exists.
-	*/
+	/* SDCARD_CLK_FB - APL EDS Vol1 remarks:
+	   This is not a physical GPIO that can be used. This Signal is not Ball out on the
+	   SoC, only the buffer exists.	*/
 	PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1),
 	PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1),	/* SDCARD_WP_1V8 */
 	PAD_CFG_TERM_GPO(GPIO_183, 1, UP_20K, DEEP),	/* SD_PWR_EN_1V8 */
@@ -71,11 +67,9 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPIO_132, NONE, DEEP, NF1),	/* provided LPSS_I2C4_SDA */
 	PAD_CFG_NF(GPIO_133, NONE, DEEP, NF1),	/* provided LPSS_I2C4_SCL */
 
-	/*
-	 * Hint for USB enable power: some GPIOs are open drain outputs,
-	 * to drive high -> Bit GPIO_TX_DIS has to be set in combination with PU
-	 * PAD_CFG_GPO macro does not work. Refer to APL EDS Vol 4.
-	 */
+	/* Hint for USB enable power: some GPIOs are open drain outputs, to drive high -> Bit
+	   GPIO_TX_DIS has to be set in combination with PU PAD_CFG_GPO macro does not work.
+	   Refer to APL EDS Vol 4. */
 	PAD_CFG_GPI(GPIO_134, UP_20K, DEEP),		/* enable USB0 power */
 	PAD_CFG_GPI(GPIO_135, UP_20K, DEEP),		/* unused */
 	PAD_CFG_GPI(GPIO_136, UP_20K, DEEP),		/* enable USB7 power */
@@ -210,8 +204,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1),/* FST_IO2 - MEM_CONFIG0 */
 	PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1),/* FST_IO3 - MEM_CONFIG1 */
 	PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1),/* FST_SPI_CLK */
-	/* FST_SPI_CLK_FB - Pad not bonded, default register value is the same
-	 * as here. Refer to Intel Doc APL EDS Vol 1 */
+	/* FST_SPI_CLK_FB - Pad not bonded, default register value is the same as here. Refer
+	   to Intel Doc APL EDS Vol 1 */
 	PAD_CFG_NF(FST_SPI_CLK_FB, NONE, DEEP, NF1),
 
 	/* SIO_SPI_0 for F-module on mainboard */
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c
index 7f4334eb9e..26fc27a601 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/lcd_panel.c
@@ -61,8 +61,8 @@ enum cb_err mainboard_ptn3460_config(struct ptn_3460_config *cfg)
 		return CB_ERR;
 	}
 
-	/* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters: */
-	/* Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */
+	/* Set up PTN3460 registers based on hwinfo and fixed board-specific parameters:
+	   Use 2 lanes for eDP, no P/N swapping, no ASSR, allow both HBR and RBR modes. */
 	cfg->dp_interface_ctrl = 0x00;
 	/* Use odd bus for LVDS clock distribution only. */
 	cfg->lvds_interface_ctrl1 = 0x01;