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authorGang Chen <gang.c.chen@intel.com>2022-07-05 21:18:05 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-03-14 20:02:49 +0000
commit07781e8268b3b3543e6fe15669aab029a45706e3 (patch)
tree2c8a6d57c5a90f58340d7e1a9ac4dde6b2174339
parent72298ae964511f355fc9f4489da278dbaf03feea (diff)
intelblocks/pmc: Assign initial values to pmc_gpe_init variables
pmc_gpe_init uses soc_get_gpi_gpe_configs to initialize dw0, dw1 and dw2. dw0, dw1 and dw2 are uninitialized before calling soc_get_gpi_gpe_configs. This is error prone for some soc implementations where soc_get_gpi_gpe_configs does nothing. This patch is simple, just to assign zero values to dw0, dw1 and dw0, to enhance the code robustness. TEST=intel/archercity CRB Signed-off-by: Gang Chen <gang.c.chen@intel.com> Change-Id: I8a710a2ac1482eed8c11977d51b187d834122d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81210 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/common/block/pmc/pmclib.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index c58b3a444b..054e731e45 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -581,7 +581,7 @@ void pmc_gpe_init(void)
{
uint32_t gpio_cfg = 0;
uint32_t gpio_cfg_reg;
- uint8_t dw0, dw1, dw2;
+ uint8_t dw0 = 0, dw1 = 0, dw2 = 0;
/* Read PMC base address from soc. This is implemented in soc */
uintptr_t pmc_bar = soc_read_pmc_base();