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authorSubrata Banik <subratabanik@google.com>2024-06-17 12:47:21 +0530
committerSubrata Banik <subratabanik@google.com>2024-06-18 08:25:17 +0000
commit04fd591b082214618875054bbb3a0c9775f8cf75 (patch)
treed89d2d98be53416c69c4d538cb7253110b9130f7
parent5acdfa23fd4277bd46067ef5bdc2d6a175a38987 (diff)
cpu/x86: Rename `PDE_table` to `PDPT` for 1 GiB page mappings
This commit fixes an incorrect variable name in the page table setup for 1 GiB pages. The label PDE_table was used when it should have been PDPT, as it represents a "Page Directory Pointer Table (PDPT)", not a "Page Directory Table (PDT) or PDE_Table". This change ensures correct nomenclature and consistency in the code. PML4 -> PDPT --------> 1GB Physical Page As per x86-64 specification, 1GB pages bypass the Page Directory Table (PDT) level of the page table hierarchy, mapping directly from the Page Directory Pointer (PDPT) Table to the physical page. Change-Id: I1e1064653a265215054f31f0e4e46bf8200ca471 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83100 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
-rw-r--r--src/cpu/x86/64bit/pt1G.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index 3ddb620eaa..3502964d15 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -20,10 +20,10 @@
.global PM4LE
.align 4096
PM4LE:
-.quad _GEN_DIR(PDE_table)
+.quad _GEN_DIR(PDPT)
.align 4096
-PDE_table: /* identity map 1GiB pages * 512 */
+PDPT: /* identity map 1GiB pages * 512 */
.rept 512
-.quad _GEN_PAGE(0x40000000 * ((. - PDE_table) >> 3))
+.quad _GEN_PAGE(0x40000000 * ((. - PDPT) >> 3))
.endr