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authorAamir Bohra <aamir.bohra@intel.com>2018-12-26 18:50:17 +0530
committerShelley Chen <shchen@google.com>2018-12-27 22:08:57 +0000
commit049ad67f76a7cd051f3228e084d0097d8cef8249 (patch)
treeec02f0a291ea5aa1c2f1a401b0097d8e332e4e1f
parent04a7ce728d83a6e0407c5627b01c6c64f260808a (diff)
mb/google/hatch: Add SMI handlers
Add SMI handlers for below SMI events: 1. eSPI SMI event. 2. ACPI enable/disable SMI event -> Add support for EC to configure SMI mask on ACPI disable. -> Add support for EC to configure SCI mask on ACPI enable. 3. Sleep(S3/S5) SMI event -> Add support for EC to configure wake mask for S3/S5 event Change-Id: I7127b44712cd89b3d583e9948698870ca0c64b2b Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/30443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
-rw-r--r--src/mainboard/google/hatch/smihandler.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/smihandler.c b/src/mainboard/google/hatch/smihandler.c
index f8f43eb8fb..68ef155423 100644
--- a/src/mainboard/google/hatch/smihandler.c
+++ b/src/mainboard/google/hatch/smihandler.c
@@ -12,3 +12,26 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <soc/smm.h>
+#include <variant/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}