diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-01 23:38:19 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 13:59:17 +0000 |
| commit | 03a6ccd20d9bb54e3a009269b8e454ee8a2e3051 (patch) | |
| tree | 8f8b9c6fc6e383e5e7aa4f9631119a8517859d04 | |
| parent | 1a010236cf922fc28cfb36b604bdf17a9ea3cb82 (diff) | |
sb/amd: Remove dropped platforms
This code is now unused by any platform.
Change-Id: I60afbde6ead70f0c887866fc351b4a6a15a89287
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69120
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
122 files changed, 1 insertions, 19198 deletions
diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c index b819dff50b..15cdeeae13 100644 --- a/src/drivers/amd/agesa/state_machine.c +++ b/src/drivers/amd/agesa/state_machine.c @@ -291,10 +291,6 @@ static void amd_bs_dev_enable(void *arg) if (!acpi_is_wakeup_s3()) agesa_execute_state(cb, AMD_INIT_MID); - - /* FIXME */ - if (CONFIG(AMD_SB_CIMX) && acpi_is_wakeup_s3()) - sb_After_Pci_Restore_Init(); } static void amd_bs_post_device(void *arg) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index d88c459400..6c77d21cf2 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -87,8 +87,6 @@ void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); /* FCH callouts, not used with CIMx. */ #define HAS_AGESA_FCH_OEM_CALLOUT \ - CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) || \ - CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) || \ CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || \ CONFIG(SOUTHBRIDGE_AMD_PI_KERN) diff --git a/src/southbridge/amd/agesa/Kconfig b/src/southbridge/amd/agesa/Kconfig deleted file mode 100644 index 1627a7a8b0..0000000000 --- a/src/southbridge/amd/agesa/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -source "src/southbridge/amd/agesa/hudson/Kconfig" diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc deleted file mode 100644 index 21985561bd..0000000000 --- a/src/southbridge/amd/agesa/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig deleted file mode 100644 index 5ea6b1a2e0..0000000000 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ /dev/null @@ -1,180 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config SOUTHBRIDGE_AMD_AGESA_HUDSON - bool - -config SOUTHBRIDGE_AMD_AGESA_YANGTZE - bool - -if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE - -config SOUTHBRIDGE_SPECIFIC_OPTIONS - def_bool y - select HAVE_USBDEBUG_OPTIONS - select HAVE_CF9_RESET - select HAVE_CF9_RESET_PREPARE - select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_ACPIMMIO - select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM - select SOC_AMD_COMMON_BLOCK_PCI_MMCONF - select BOOT_DEVICE_SUPPORTS_WRITES - -config EHCI_BAR - hex - default 0xfef00000 - -config HUDSON_XHCI_ENABLE - bool "Enable Hudson XHCI Controller" - default y if HUDSON_XHCI_FWM - help - The XHCI controller must be enabled and the XHCI firmware - must be added in order to have USB 3.0 support configured - by coreboot. The OS will be responsible for enabling the XHCI - controller if the XHCI firmware is available but the - XHCI controller is not enabled by coreboot. - -config HUDSON_XHCI_FWM - bool "Add xhci firmware" - default y if USE_BLOBS - help - Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 - -config HUDSON_IMC_ENABLE - bool - default n - -config HUDSON_IMC_FWM - bool "Add IMC firmware" - depends on HUDSON_IMC_ENABLE - default y if USE_BLOBS - select SPI_FLASH_HAS_VOLATILE_GROUP if SPI_FLASH - help - Add Hudson 2/3/4 IMC Firmware to support the onboard fan control - -config HUDSON_GEC_FWM - bool - default n - help - Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. - Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. - -config HUDSON_XHCI_FWM_FILE - string "XHCI firmware path and filename" - default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE - depends on HUDSON_XHCI_FWM - -config HUDSON_IMC_FWM_FILE - string "IMC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE - depends on HUDSON_IMC_FWM - -config HUDSON_GEC_FWM_FILE - string "GEC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE - depends on HUDSON_GEC_FWM - -config HUDSON_SATA_MODE - int "SATA Mode" - default 2 - range 0 6 - help - Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. - The default is NATIVE. - 0: NATIVE mode does not require a ROM. - 1: RAID mode must have the two ROM files. - 2: AHCI may work with or without AHCI ROM. It depends on the payload support. - For example, seabios does not require the AHCI ROM. - 3: LEGACY IDE - 4: IDE to AHCI - 5: AHCI7804: ROM Required, and AMD driver required in the OS. - 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. - -comment "NATIVE" - depends on HUDSON_SATA_MODE = 0 - -comment "RAID" - depends on HUDSON_SATA_MODE = 1 - -comment "AHCI" - depends on HUDSON_SATA_MODE = 2 - -comment "LEGACY IDE" - depends on HUDSON_SATA_MODE = 3 - -comment "IDE to AHCI" - depends on HUDSON_SATA_MODE = 4 - -comment "AHCI7804" - depends on HUDSON_SATA_MODE = 5 - -comment "IDE to AHCI7804" - depends on HUDSON_SATA_MODE = 6 - -if HUDSON_SATA_MODE = 2 || HUDSON_SATA_MODE = 5 - -config AHCI_ROM_ID - string "AHCI device PCI IDs" - default "1022,7801" if HUDSON_SATA_MODE = 2 - default "1022,7804" if HUDSON_SATA_MODE = 5 - -config HUDSON_AHCI_ROM - bool "Add a AHCI ROM" - -config AHCI_ROM_FILE - string "AHCI ROM path and filename" - depends on HUDSON_AHCI_ROM - default "src/southbridge/amd/agesa/hudson/ahci.bin" - -endif - -if HUDSON_SATA_MODE = 1 - -config RAID_ROM_ID - string "RAID device PCI IDs" - default "1022,7802" - help - 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode - -config RAID_ROM_FILE - string "RAID ROM path and filename" - default "src/southbridge/amd/agesa/hudson/raid.bin" - -config RAID_MISC_ROM_FILE - string "RAID Misc ROM path and filename" - default "src/southbridge/amd/agesa/hudson/misc.bin" - -config RAID_MISC_ROM_POSITION - hex "RAID Misc ROM Position" - default 0xFFF00000 - help - The RAID ROM requires that the MISC ROM is located between the range - 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. - The CONFIG_ROM_SIZE must be larger than 0x100000. - -endif - -config HUDSON_LEGACY_FREE - bool "System is legacy free" - help - Select y if there is no keyboard controller in the system. - This sets variables in AGESA and ACPI. - -config ACPI_ENABLE_THERMAL_ZONE - bool - default y - -endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE - -if SOUTHBRIDGE_AMD_AGESA_YANGTZE - config AZ_PIN - hex - default 0xaa - help - bit 1,0 - pin 0 - bit 3,2 - pin 1 - bit 5,4 - pin 2 - bit 7,6 - pin 3 -endif diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc deleted file mode 100644 index b8eb5b9b37..0000000000 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ /dev/null @@ -1,79 +0,0 @@ - -CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/agesa/hudson -CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/agesa/hudson - -romstage-y += smbus.c smbus_spd.c -ramstage-y += hudson.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += sm.c -ramstage-y += ide.c -ramstage-y += sata.c -ramstage-y += hda.c -ramstage-y += pci.c -ramstage-y += pcie.c -ramstage-y += sd.c - -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c - -bootblock-y += bootblock.c -bootblock-y += early_setup.c -bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c - -romstage-y += enable_usbdebug.c -ramstage-y += enable_usbdebug.c -romstage-y += early_setup.c - -ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-y += resume.c ramtop.c - -romstage-y += ramtop.c -postcar-y += ramtop.c - -romstage-y += imc.c -ramstage-y += imc.c - -all-y += reset.c - -smm-y += smihandler.c smi_util.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c - -# ROMSIG At ROMBASE + 0x20000: -# +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address |USB3 ROM | -# +-----------+---------------+----------------+------------+ -# EC ROM should be 64K aligned. - -HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) - -ifdef CONFIG_HUDSON_AHCI_ROM -stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) -cbfs-files-y += pci$(stripped_ahci_rom_id).rom -pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) -pci$(stripped_ahci_rom_id).rom-type := optionrom -pci$(stripped_ahci_rom_id).rom-required := Hudson AHCI Option ROM (Contact your AMD representative) -endif - -add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), ) - -OPT_HUDSON_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_XHCI_FWM_FILE), --xhci) -OPT_HUDSON_IMC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_IMC_FWM_FILE), --imc) -OPT_HUDSON_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_HUDSON_GEC_FWM_FILE), --gec) - -$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ - $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ - $(AMDFWTOOL) - rm -f $@ - @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ - $(OPT_HUDSON_XHCI_FWM_FILE) \ - $(OPT_HUDSON_IMC_FWM_FILE) \ - $(OPT_HUDSON_GEC_FWM_FILE) \ - --flashsize $(CONFIG_ROM_SIZE) \ - --output $@ - -cbfs-files-y += apu/amdfw -apu/amdfw-file := $(obj)/amdfw.rom -apu/amdfw-position := $(HUDSON_FWM_POSITION) -apu/amdfw-type := raw diff --git a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl b/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl deleted file mode 100644 index 6fe5e33cb8..0000000000 --- a/src/southbridge/amd/agesa/hudson/acpi/AmdImc.asl +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -OperationRegion(IMIO, SystemIO, 0x3E, 0x02) -Field(IMIO , ByteAcc, NoLock, Preserve) { - IMCX,8, - IMCA,8 -} - -IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { - Offset(0x80), - MSTI, 8, - MITS, 8, - MRG0, 8, - MRG1, 8, - MRG2, 8, - MRG3, 8, -} - -Method(WACK, 0) -{ - Local0 = 0 - Local1 = 50 - While ((Local0 != 0xfa) && (Local1 > 0)) { - Local0 = MRG0 - Sleep(10) - Local1-- - } -} - -//Init -Method (ITZE, 0) -{ - MRG0 = 0 - MRG1 = 0xb5 - MRG2 = 0 - MSTI = 0x96 - WACK() - - MRG0 = 0 - MRG1 = 0 - MRG2 = 0 - MSTI = 0x80 - WACK() - - Local0 = MRG2 | 0x01 - - MRG0 = 0 - MRG1 = 0 - MRG2 = Local0 - MSTI = 0x81 - WACK() -} diff --git a/src/southbridge/amd/agesa/hudson/acpi/audio.asl b/src/southbridge/amd/agesa/hudson/acpi/audio.asl deleted file mode 100644 index 58f566e70b..0000000000 --- a/src/southbridge/amd/agesa/hudson/acpi/audio.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device(AZHD) { /* 0:14.2 - HD Audio */ - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method (_INI, 0, NotSerialized) - { - NSEN = 0 - NSDO = 1 - NSDI = 1 - } -} /* end AZHD */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl deleted file mode 100644 index b87b9e4946..0000000000 --- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl +++ /dev/null @@ -1,166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* System Bus */ -/* _SB.PCI0 */ - -/* Operating System Capabilities Method */ -Method(_OSC,4) -{ - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) - { - /* Let OS control everything */ - Return (Arg3) - } Else { - CreateDWordField(Arg3,0,CDW1) - CDW1 |= 4 // Unrecognized UUID - Return (Arg3) - } -} - -/* Describe the Southbridge devices */ - -/* 0:11.0 - SATA */ -Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" -} /* end STCR */ - -/* 0:14.0 - SMBUS */ -Device(SBUS) { - Name(_ADR, 0x00140000) -} /* end SBUS */ - -#include "usb.asl" - -/* 0:14.2 - HD Audio */ -#include "audio.asl" - -/* 0:14.3 - LPC */ -#include "lpc.asl" - -/* 0:14.7 - SD Controller */ -Device(SDCN) { - Name(_ADR, 0x00140007) -} /* end SDCN */ - -#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - -/* 0:14.4 - PCI slot 1, 2, 3 */ -Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } -} - -/* 0:14.6 - GEC Controller */ -Device(ACMD) { - Name(_ADR, 0x00140006) -} /* end Ac97modem */ -#endif - -Name(CRES, ResourceTemplate() { - /* Set the Bus number and Secondary Bus number for the PCI0 device - * The Secondary bus range for PCI0 lets the system - * know what bus values are allowed on the downstream - * side of this PCI bus if there is a PCI-PCI bridge. - * PCI buses can have 256 secondary buses which - * range from [0-0xFF] but they do not need to be - * sequential. - */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00FF, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x03B0, /* range minimum */ - 0x03DF, /* range maximum */ - 0x0000, /* translation */ - 0x0030 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) -}) /* End Name(_SB.PCI0.CRES) */ - -Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - MM1B = TOM1 - Local0 = 0x10000000 << 4 - Local0 -= TOM1 - MM1L = Local0 - - Return (CRES) /* note to change the Name buffer */ -} /* end of Method(_SB.PCI0._CRS) */ - -#if CONFIG(HUDSON_IMC_FWM) - #include "acpi/AmdImc.asl" /* Hudson IMC function */ -#endif - -/* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ -Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - -#if CONFIG(HUDSON_IMC_FWM) -#if CONFIG(ACPI_ENABLE_THERMAL_ZONE) - ITZE() /* enable IMC Fan Control*/ -#endif -#endif -} /* End Method(_SB._INI) */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl b/src/southbridge/amd/agesa/hudson/acpi/lpc.asl deleted file mode 100644 index 6d723a99a3..0000000000 --- a/src/southbridge/amd/agesa/hudson/acpi/lpc.asl +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* 0:14.3 - LPC */ -Device(LIBR) { - Name(_ADR, 0x00140003) - /* Method(_INI) { - * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") - } */ /* End Method(_SB.SBRDG._INI) */ - - OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space - Field(CFG,DWordAcc,NoLock,Preserve){ - Offset(0xA0), - BAR,32} // SPI Controller Base Address Register (Index 0xA0) - - Device(LDRC) // LPC device: Resource consumption - { - Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources - Name (CRS, ResourceTemplate () // Current Motherboard resources - { - Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address - 0x00000000, // Address Base - 0x00000000, // Address Length - BAR0 // Descriptor Name - ) - }) - - Method(_CRS,0,NotSerialized) - { - CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address - CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length - Store(BAR,SPIB) // SPI base address mapped - Store(0x1000,SPIL) // 4k space mapped - Return(CRS) - } - } - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - #include "acpi/superio.asl" -} /* end LIBR */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl deleted file mode 100644 index 6ff81cd66f..0000000000 --- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl +++ /dev/null @@ -1,442 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRA - Return (IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_SRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRA = Local0 - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRB - Return (IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRB = Local0 - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRC - Return (IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRC = Local0 - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRD - Return (IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRD = Local0 - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRE - Return (IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRE = Local0 - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return (PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRF - Return (IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRF = Local0 - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRG - Return (IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRG = Local0 - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRH - Return (IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRH = Local0 - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl b/src/southbridge/amd/agesa/hudson/acpi/pcie.asl deleted file mode 100644 index 294323fc0e..0000000000 --- a/src/southbridge/amd/agesa/hudson/acpi/pcie.asl +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - /* PCI IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } - - /* Client Management index/data registers */ - OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, - } - - /* GPM Port register */ - OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, - } - - /* Flash ROM program enable register */ - OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, - } - - /* PM2 index/data registers */ - OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, - } - - /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ - OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, - } - - IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - Offset(0xEE), - UPWS, 3, - } diff --git a/src/southbridge/amd/agesa/hudson/acpi/smbus.asl b/src/southbridge/amd/agesa/hudson/acpi/smbus.asl deleted file mode 100644 index 16990d45f4..0000000000 --- a/src/southbridge/amd/agesa/hudson/acpi/smbus.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: CC-PDDC */ - -/* Please update the license if adding licensable material. */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/usb.asl b/src/southbridge/amd/agesa/hudson/acpi/usb.asl deleted file mode 100644 index 399ce6eecb..0000000000 --- a/src/southbridge/amd/agesa/hudson/acpi/usb.asl +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* 0:12.0 - OHCI */ -Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH1 */ - -/* 0:12.2 - EHCI */ -Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH2 */ - -/* 0:13.0 - OHCI */ -Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH3 */ - -/* 0:13.2 - EHCI */ -Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH4 */ - -/* 0:16.0 - OHCI */ -Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH5 */ - -/* 0:16.2 - EHCI */ -Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH5 */ - -#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) -/* 0:14.5 - OHCI */ -Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) -} /* end UEH1 */ -#endif - -/* 0:10.0 - XHCI 0*/ -Device(XHC0) { - Name(_ADR, 0x00100000) - Name(_PRW, Package() {0x0B, 4}) -} /* end XHC0 */ - -#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) -/* 0:10.1 - XHCI 1*/ -Device(XHC1) { - Name(_ADR, 0x00100001) - Name(_PRW, Package() {0x0B, 4}) -} /* end XHC1 */ -#endif diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h deleted file mode 100644 index 20c15f0cdd..0000000000 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_PCI_INT_DEFS_H -#define AMD_PCI_INT_DEFS_H - -/* - * PIRQ and device routing - these define the index - * into the FCH PCI_INTR 0xC00/0xC01 interrupt - * routing table - */ -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define FCH_INT_TABLE_SIZE 0x54 -#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) -#define FCH_INT_TABLE_SIZE 0x42 -#endif - -#define PIRQ_NC 0x1F /* Not Used */ -#define PIRQ_A 0x00 /* INT A */ -#define PIRQ_B 0x01 /* INT B */ -#define PIRQ_C 0x02 /* INT C */ -#define PIRQ_D 0x03 /* INT D */ -#define PIRQ_E 0x04 /* INT E */ -#define PIRQ_F 0x05 /* INT F */ -#define PIRQ_G 0x06 /* INT G */ -#define PIRQ_H 0x07 /* INT H */ -#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ -#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ -#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ -#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ -#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ -#define PIRQ_SCI 0x10 /* SCI IRQ */ -#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ -#define PIRQ_ASF 0x12 /* ASF */ -#define PIRQ_HDA 0x13 /* HDA 14h.2 */ -#define PIRQ_FC 0x14 /* FC */ -#define PIRQ_GEC 0x15 /* GEC */ -#define PIRQ_PMON 0x16 /* Performance Monitor */ -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) -#define PIRQ_SD 0x17 /* SD */ -#endif -#define PIRQ_IMC0 0x20 /* IMC INT0 */ -#define PIRQ_IMC1 0x21 /* IMC INT1 */ -#define PIRQ_IMC2 0x22 /* IMC INT2 */ -#define PIRQ_IMC3 0x23 /* IMC INT3 */ -#define PIRQ_IMC4 0x24 /* IMC INT4 */ -#define PIRQ_IMC5 0x25 /* IMC INT5 */ -#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ -#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ -#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ -#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ -#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ -#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ -#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ -#define PIRQ_IDE 0x40 /* IDE 14h.1 */ -#define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define PIRQ_SD 0x42 /* SD 14h.7 */ -#define PIRQ_GPP0 0x50 /* GPP INT 0 */ -#define PIRQ_GPP1 0x51 /* GPP INT 1 */ -#define PIRQ_GPP2 0x52 /* GPP INT 2 */ -#define PIRQ_GPP3 0x53 /* GPP INT 3 */ -#endif - -#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h deleted file mode 100644 index 46200eaad4..0000000000 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_PCI_INT_TYPES_H -#define AMD_PCI_INT_TYPES_H - -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -const char *intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" -}; -#elif CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) -const char *intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", - [0x40] = "RSVD\t", "SATA\t", -}; -#endif - -#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c deleted file mode 100644 index 039712fca6..0000000000 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/bootblock.h> -#include <amdblocks/acpimmio.h> -#include <device/pci_ops.h> -#include <southbridge/amd/agesa/hudson/hudson.h> - -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The HUDSON power-on default is to map 512K ROM space. - * - */ -static void hudson_enable_rom(void) -{ - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - - /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_s_read_config8(dev, 0x48); - reg8 |= (1 << 3) | (1 << 4); - pci_s_write_config8(dev, 0x48, reg8); - - /* LPC ROM address range 1: */ - /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_s_write_config16(dev, 0x68, 0x000e); - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_s_write_config16(dev, 0x6a, 0x000f); - - /* LPC ROM address range 2: */ - /* - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_s_write_config16(dev, 0x6e, 0xffff); -} - -void bootblock_early_southbridge_init(void) -{ - u32 data; - - hudson_enable_rom(); - enable_acpimmio_decode_pm24(); - hudson_lpc_decode(); - - if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - - const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding for SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - - /* - * Enable FCH to decode TPM associated Memory and IO regions for vboot - * - * Enable decoding of TPM cycles defined in TPM 1.2 spec - * Enable decoding of legacy TPM addresses: IO addresses 0x7f- - * 0x7e and 0xef-0xee. - */ - data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE); - data |= TPM_12_EN | TPM_LEGACY_EN; - pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - pm_write8(0xd2, 0); -} diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h deleted file mode 100644 index 6eba9f2063..0000000000 --- a/src/southbridge/amd/agesa/hudson/chip.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef HUDSON_CHIP_H -#define HUDSON_CHIP_H - -struct southbridge_amd_agesa_hudson_config -{ - u8 sd_mode; -}; - -#endif /* HUDSON_CHIP_H */ diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c deleted file mode 100644 index 18bc9b22d2..0000000000 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _HUDSON_EARLY_SETUP_C_ -#define _HUDSON_EARLY_SETUP_C_ - -#include <stdint.h> -#include <amdblocks/acpimmio.h> -#include <device/pci_ops.h> - -#include "hudson.h" - -void hudson_pci_port80(void) -{ - u8 byte; - pci_devfn_t dev; - - /* P2P Bridge */ - dev = PCI_DEV(0, 0x14, 4); - - /* Chip Control: Enable subtractive decoding */ - byte = pci_read_config8(dev, 0x40); - byte |= 1 << 5; - pci_write_config8(dev, 0x40, byte); - - /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ - byte = pci_read_config8(dev, 0x4B); - byte |= 1 << 7; - pci_write_config8(dev, 0x4B, byte); - - /* The same IO Base and IO Limit here is meaningful because we set the - * bridge to be subtractive. During early setup stage, we have to make - * sure that data can go through port 0x80. - */ - /* IO Base: 0xf000 */ - byte = pci_read_config8(dev, 0x1C); - byte |= 0xF << 4; - pci_write_config8(dev, 0x1C, byte); - - /* IO Limit: 0xf000 */ - byte = pci_read_config8(dev, 0x1D); - byte |= 0xF << 4; - pci_write_config8(dev, 0x1D, byte); - - /* PCI Command: Enable IO response */ - byte = pci_read_config8(dev, 0x04); - byte |= 1 << 0; - pci_write_config8(dev, 0x04, byte); - - /* LPC controller */ - dev = PCI_DEV(0, 0x14, 3); - - byte = pci_read_config8(dev, 0x4A); - byte &= ~(1 << 5); /* disable lpc port 80 */ - pci_write_config8(dev, 0x4A, byte); -} - -void hudson_lpc_port80(void) -{ - u8 byte; - - /* Enable port 80 LPC decode in pci function 3 configuration space. */ - const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x4a); - byte |= 1 << 5; /* enable port 80 */ - pci_write_config8(dev, 0x4a, byte); -} - -void hudson_lpc_decode(void) -{ - u32 tmp; - - /* Enable LPC controller */ - pm_write8(0xec, pm_read8(0xec) | 0x01); - - const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - /* Serial port enumeration on Hudson: - * PORT0 - 0x3f8 - * PORT1 - 0x2f8 - * PORT5 - 0x2e8 - * PORT7 - 0x3e8 - */ - tmp = DECODE_ENABLE_SERIAL_PORT0 | DECODE_ENABLE_SERIAL_PORT1 - | DECODE_ENABLE_SERIAL_PORT5 | DECODE_ENABLE_SERIAL_PORT7; - - pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, tmp); -} - -#endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c b/src/southbridge/amd/agesa/hudson/enable_usbdebug.c deleted file mode 100644 index 9dda666fe1..0000000000 --- a/src/southbridge/amd/agesa/hudson/enable_usbdebug.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <device/pci_ehci.h> -#include <device/pci_def.h> -#include "hudson.h" - -#define DEBUGPORT_MISC_CONTROL 0x80 - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - /* Enable all of the USB controllers */ - outb(0xEF, PM_INDEX); - outb(0x7F, PM_DATA); - - if (hcd_idx == 3) - return PCI_DEV(0, 0x16, 2); - else if (hcd_idx == 2) - return PCI_DEV(0, 0x13, 2); - else - return PCI_DEV(0, 0x12, 2); -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u8 *base_regs = pci_ehci_base_regs(dev); - u32 reg32; - - /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ - reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); - reg32 &= ~(0xf << 28); - reg32 |= (port << 28); - reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ - write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); -} diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c deleted file mode 100644 index 2b39bcd043..0000000000 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include <console/console.h> -#include <acpi/acpi.h> -#include <device/device.h> -#include <version.h> - -#include "hudson.h" -#include "smi.h" - -#if CONFIG(HUDSON_LEGACY_FREE) - #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE -#else - #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) -#endif - -/* - * Reference section 5.2.9 Fixed ACPI Description Table (FADT) - * in the ACPI 3.0b specification. - */ -void acpi_fill_fadt(acpi_fadt_t *fadt) -{ - printk(BIOS_DEBUG, "pm_base: 0x%04x\n", HUDSON_ACPI_IO_BASE); - - fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ - - if (permanent_smi_handler()) { - fadt->smi_cmd = ACPI_SMI_CTL_PORT; - fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; - fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; - } - - fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; - fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; - fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; - fadt->gpe0_blk = ACPI_GPE0_BLK; - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ - fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ - fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_PLATFORM_CLOCK | - ACPI_FADT_S4_RTC_VALID | - ACPI_FADT_REMOTE_POWER_ON; - - fadt->ARM_boot_arch = 0; /* Must be zero if ACPI Revision <= 5.0 */ - - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; /* EventStatus + Event Enable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; -} diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c deleted file mode 100644 index a63d52a8d2..0000000000 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> - -#include "hudson.h" - -static void hda_init(struct device *dev) -{ -} - -static struct device_operations hda_audio_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = hda_init, - .ops_pci = &pci_dev_ops_pci, -}; - -static const struct pci_driver hdaaudio_driver __pci_driver = { - .ops = &hda_audio_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_HDA, -}; diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c deleted file mode 100644 index 0c96ec15a3..0000000000 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> -#include <device/mmio.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <types.h> - -#include "hudson.h" -#include "imc.h" -#include "smbus.h" -#include "smi.h" - -#define PM_REG_USB_ENABLE 0xef - -enum usb_enable { - USB_EN_DEVFN_12_0 = (1 << 0), - USB_EN_DEVFN_12_2 = (1 << 1), - USB_EN_DEVFN_13_0 = (1 << 2), - USB_EN_DEVFN_13_2 = (1 << 3), - USB_EN_DEVFN_16_0 = (1 << 4), - USB_EN_DEVFN_16_2 = (1 << 5), -}; - -static void hudson_disable_usb(u8 disable) -{ - u8 reg8; - - /* Bit 7 handles routing, 6 is reserved. we don't mess with those */ - disable &= 0x3f; - - reg8 = pm_read8(PM_REG_USB_ENABLE); - reg8 &= ~disable; - pm_write8(PM_REG_USB_ENABLE, reg8); -} - -void hudson_enable(struct device *dev) -{ - printk(BIOS_DEBUG, "%s()\n", __func__); - switch (dev->path.pci.devfn) { - case PCI_DEVFN(0x14, 5): - if (dev->enabled == 0) { - u32 usb_device_id = pci_read_config16(dev, PCI_DEVICE_ID); - u8 reg8; - if (usb_device_id == PCI_DID_AMD_SB900_USB_20_5) { - /* turn off and remove device 0:14.5 from PCI space */ - reg8 = pm_read8(0xef); - reg8 &= ~BIT(6); - pm_write8(0xef, reg8); - } - } - break; - - case PCI_DEVFN(0x14, 7): - if (dev->enabled == 0) { - u32 sd_device_id = pci_read_config16(dev, PCI_DEVICE_ID); - /* turn off the SDHC controller in the PM reg */ - u8 reg8; - if (sd_device_id == PCI_DID_AMD_HUDSON_SD) { - reg8 = pm_read8(0xe7); - reg8 &= ~BIT(0); - pm_write8(0xe7, reg8); - } else if (sd_device_id == PCI_DID_AMD_YANGTZE_SD) { - reg8 = pm_read8(0xe8); - reg8 &= ~BIT(0); - pm_write8(0xe8, reg8); - } - /* remove device 0:14.7 from PCI space */ - reg8 = pm_read8(0xd3); - reg8 &= ~BIT(6); - pm_write8(0xd3, reg8); - } - break; - - /* Make sure to disable other functions if function 0 is disabled */ - case PCI_DEVFN(0x12, 0): - if (dev->enabled == 0) - hudson_disable_usb(USB_EN_DEVFN_12_0); - __fallthrough; - case PCI_DEVFN(0x12, 2): - if (dev->enabled == 0) - hudson_disable_usb(USB_EN_DEVFN_12_2); - break; - case PCI_DEVFN(0x13, 0): - if (dev->enabled == 0) - hudson_disable_usb(USB_EN_DEVFN_13_0); - __fallthrough; - case PCI_DEVFN(0x13, 2): - if (dev->enabled == 0) - hudson_disable_usb(USB_EN_DEVFN_13_2); - break; - case PCI_DEVFN(0x16, 0): - if (dev->enabled == 0) - hudson_disable_usb(USB_EN_DEVFN_16_0); - __fallthrough; - case PCI_DEVFN(0x16, 2): - if (dev->enabled == 0) - hudson_disable_usb(USB_EN_DEVFN_16_2); - break; - default: - break; - } -} - -static void hudson_init_acpi_ports(void) -{ - /* We use some of these ports in SMM regardless of whether or not - * ACPI tables are generated. Enable these ports indiscriminately. - */ - - pm_write16(0x60, ACPI_PM_EVT_BLK); - pm_write16(0x62, ACPI_PM1_CNT_BLK); - pm_write16(0x64, ACPI_PM_TMR_BLK); - pm_write16(0x68, ACPI_GPE0_BLK); - /* CpuControl is in \_PR.CP00, 6 bytes */ - pm_write16(0x66, ACPI_CPU_CONTROL); - - if (CONFIG(HAVE_SMI_HANDLER)) { - pm_write16(0x6a, ACPI_SMI_CTL_PORT); - hudson_enable_acpi_cmd_smi(); - } else { - pm_write16(0x6a, 0); - } - - /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers - * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn - */ - pm_write8(0x74, BIT(0) | BIT(1) | BIT(4) | BIT(2)); -} - -static void hudson_init(void *chip_info) -{ - hudson_init_acpi_ports(); -} - -static void hudson_final(void *chip_info) -{ - /* AMD AGESA does not enable thermal zone, so we enable it here. */ - if (CONFIG(HUDSON_IMC_FWM) && !CONFIG(ACPI_ENABLE_THERMAL_ZONE)) - enable_imc_thermal_zone(); -} - -struct chip_operations southbridge_amd_agesa_hudson_ops = { - CHIP_NAME("ATI HUDSON") - .enable_dev = hudson_enable, - .init = hudson_init, - .final = hudson_final -}; diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h deleted file mode 100644 index eeb60ca35a..0000000000 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef HUDSON_H -#define HUDSON_H - -#include <device/device.h> -#include <types.h> - -/* Power management index/data registers */ -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 -#define PM2_INDEX 0xcd0 -#define PM2_DATA 0xcd1 - -#define HUDSON_ACPI_IO_BASE 0x800 - -#define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ -#define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ -#define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ -#define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ -#define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ - -#define ACPI_SMI_CTL_PORT 0xb2 -#define ACPI_SMI_CMD_CST_CONTROL 0xde -#define ACPI_SMI_CMD_PST_CONTROL 0xad -#define ACPI_SMI_CMD_DISABLE 0xbe -#define ACPI_SMI_CMD_ENABLE 0xef -#define ACPI_SMI_CMD_S4_REQ 0xc0 - -#define REV_HUDSON_A11 0x11 -#define REV_HUDSON_A12 0x12 - -#define LPC_IO_PORT_DECODE_ENABLE 0x44 -#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) -#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) -#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) -#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) -#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) -#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) -#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) -#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) -#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) -#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) -#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) -#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) -#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) -#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) -#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) -#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) -#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) -#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) -#define DECODE_ENABLE_MIDI_PORT0 BIT(18) -#define DECODE_ENABLE_MIDI_PORT1 BIT(19) -#define DECODE_ENABLE_MIDI_PORT2 BIT(20) -#define DECODE_ENABLE_MIDI_PORT3 BIT(21) -#define DECODE_ENABLE_MSS_PORT0 BIT(22) -#define DECODE_ENABLE_MSS_PORT1 BIT(23) -#define DECODE_ENABLE_MSS_PORT2 BIT(24) -#define DECODE_ENABLE_MSS_PORT3 BIT(25) -#define DECODE_ENABLE_FDC_PORT0 BIT(26) -#define DECODE_ENABLE_FDC_PORT1 BIT(27) -#define DECODE_ENABLE_GAME_PORT BIT(28) -#define DECODE_ENABLE_KBC_PORT BIT(29) -#define DECODE_ENABLE_ACPIUC_PORT BIT(30) -#define DECODE_ENABLE_ADLIB_PORT BIT(31) - -#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 - -#define LPC_TRUSTED_PLATFORM_MODULE 0x7c -#define TPM_12_EN BIT(0) -#define TPM_LEGACY_EN BIT(2) - -#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 -#define SPI_ROM_ENABLE 0x02 -#define SPI_BASE_ADDRESS 0xFEC10000 - -static inline int hudson_sata_enable(void) -{ - /* True if IDE or AHCI. */ - return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2); -} - -static inline int hudson_ide_enable(void) -{ - /* True if IDE or LEGACY IDE. */ - return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); -} - -void hudson_lpc_port80(void); -void hudson_pci_port80(void); -void hudson_lpc_decode(void); -void hudson_clk_output_48Mhz(void); - -void hudson_enable(struct device *dev); - -#endif /* HUDSON_H */ diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c deleted file mode 100644 index eaf40b5888..0000000000 --- a/src/southbridge/amd/agesa/hudson/ide.c +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "hudson.h" - -static void ide_init(struct device *dev) -{ -} - -static struct device_operations ide_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ide_init, - .ops_pci = &pci_dev_ops_pci, -}; - -static const struct pci_driver ide_driver __pci_driver = { - .ops = &ide_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_IDE, -}; diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c deleted file mode 100644 index b1a71f3f32..0000000000 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ /dev/null @@ -1,70 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "imc.h" -#include <amdblocks/acpimmio.h> -#include <device/mmio.h> -#include <Porting.h> -#include <AGESA.h> -#include <amdlib.h> -#include <Proc/Fch/Fch.h> -#include <Proc/Fch/Common/FchCommonCfg.h> -#include <Proc/Fch/FchPlatform.h> - -void imc_reg_init(void) -{ - /* Init Power Management Block 2 (PM2) Registers. - * Check BKDG for AMD Family 16h for details. */ - pm2_write8(0, 0x06); - pm2_write8(1, 0x06); - pm2_write8(2, 0xf7); - pm2_write8(3, 0xff); - pm2_write8(4, 0xff); - -#if !CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - pm2_write8(0x10, 0x06); - pm2_write8(0x11, 0x06); - pm2_write8(0x12, 0xf7); - pm2_write8(0x13, 0xff); - pm2_write8(0x14, 0xff); -#endif - -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - UINT8 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 0x3, 0x1E4); - LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader); - PciData &= (UINT8)0x8F; - PciData |= 0x10; - LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader); -#endif -} - -void enable_imc_thermal_zone(void) -{ - AMD_CONFIG_PARAMS StdHeader; - UINT8 FunNum; - UINT8 regs[10]; - int i; - - regs[0] = 0; - regs[1] = 0; - FunNum = Fun_80; - for (i = 0; i <= 1; i++) - WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); - WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number - WaitForEcLDN9MailboxCmdAck(&StdHeader); - - for (i = 2; i < ARRAY_SIZE(regs); i++) - ReadECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); - - /* enable thermal zone 0 */ - regs[2] |= 1; - regs[0] = 0; - regs[1] = 0; - FunNum = Fun_81; - for (i = 0; i < ARRAY_SIZE(regs); i++) - WriteECmsg(MSG_REG0 + i, AccessWidth8, ®s[i], &StdHeader); - WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number - WaitForEcLDN9MailboxCmdAck(&StdHeader); -} diff --git a/src/southbridge/amd/agesa/hudson/imc.h b/src/southbridge/amd/agesa/hudson/imc.h deleted file mode 100644 index 29e7fd79b6..0000000000 --- a/src/southbridge/amd/agesa/hudson/imc.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef HUDSON_IMC_H -#define HUDSON_IMC_H - -void imc_reg_init(void); -void enable_imc_thermal_zone(void); - -#endif diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c deleted file mode 100644 index 2efc5bc2a5..0000000000 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ /dev/null @@ -1,348 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pnp.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <pc80/mc146818rtc.h> -#include <pc80/isa-dma.h> -#include <arch/io.h> -#include <arch/ioapic.h> -#include <acpi/acpi.h> -#include <pc80/i8254.h> -#include <pc80/i8259.h> -#include "hudson.h" -#include "pci_devs.h" - -static void lpc_init(struct device *dev) -{ - u8 byte; - u32 dword; - struct device *sm_dev; - - /* Enable the LPC Controller */ - sm_dev = pcidev_on_root(0x14, 0); - dword = pci_read_config32(sm_dev, 0x64); - dword |= 1 << 20; - pci_write_config32(sm_dev, 0x64, dword); - - /* Initialize isa dma */ - isa_dma_init(); - - /* Enable DMA transaction on the LPC bus */ - byte = pci_read_config8(dev, 0x40); - byte |= (1 << 2); - pci_write_config8(dev, 0x40, byte); - - /* Disable the timeout mechanism on LPC */ - byte = pci_read_config8(dev, 0x48); - byte &= ~(1 << 7); - pci_write_config8(dev, 0x48, byte); - - /* Disable LPC MSI Capability */ - byte = pci_read_config8(dev, 0x78); - byte &= ~(1 << 1); - byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going - on on LPC, it holds PCI grant, so no LPC slave cycle can - interrupt and visit LPC. */ - pci_write_config8(dev, 0x78, byte); - - /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ - /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ - byte = pci_read_config8(dev, 0xBB); - byte |= 1 << 0 | 1 << 3; - pci_write_config8(dev, 0xBB, byte); - - cmos_check_update_date(); - - /* - * Initialize the real time clock. - * The 0 argument tells cmos_init not to - * update CMOS unless it is invalid. - * 1 tells cmos_init to always initialize the CMOS. - */ - cmos_init(0); - - /* Initialize i8259 pic */ - setup_i8259(); - - /* Initialize i8254 timers */ - setup_i8254(); -} - -static void hudson_lpc_read_resources(struct device *dev) -{ - struct resource *res; - - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add a memory resource for the SPI BAR. */ - mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); - - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - compact_resources(dev); -} - -static void hudson_lpc_set_resources(struct device *dev) -{ - struct resource *res; - - /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, 2); - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); - - pci_dev_set_resources(dev); -} - -/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -static void hudson_lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_x; - int var_num = 0; - u16 reg_var[3]; - u16 reg_size[1] = {512}; - u8 wiosize = pci_read_config8(dev, 0x74); - - /* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit, - * do it like this for all regions < 16 bytes. If there is a resource > 16 bytes - * it must be 512 bytes to be able to allocate the fresh LPC window. - * - * AGESA likes to enable already one LPC region in wide port base 0x64-0x65, - * using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size - * The code tries to check if resource can fit into this region - */ - - reg = pci_read_config32(dev, 0x44); - reg_x = pci_read_config32(dev, 0x48); - - /* check if ranges are free and not use them if entry is just already taken */ - if (reg_x & (1 << 2)) - var_num = 1; - /* just in case check if someone did not manually set other ranges too */ - if (reg_x & (1 << 24)) - var_num = 2; - - if (reg_x & (1 << 25)) - var_num = 3; - - /* check AGESA region size */ - if (wiosize & (1 << 0)) - reg_size[0] = 16; - - reg_var[2] = pci_read_config16(dev, 0x90); - reg_var[1] = pci_read_config16(dev, 0x66); - reg_var[0] = pci_read_config16(dev, 0x64); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - u32 base, end; /* don't need long long */ - u32 rsize, set = 0, set_x = 0; - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; - end = resource_end(res); - /* find a resource size */ - printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); - switch (base) { - case 0x60: /* KB */ - case 0x64: /* MS */ - set |= (1 << 29); - rsize = 1; - break; - case 0x3f8: /* COM1 */ - set |= (1 << 6); - rsize = 8; - break; - case 0x2f8: /* COM2 */ - set |= (1 << 7); - rsize = 8; - break; - case 0x378: /* Parallel 1 */ - set |= (1 << 0); - set |= (1 << 1); /* + 0x778 for ECP */ - rsize = 8; - break; - case 0x3f0: /* FD0 */ - set |= (1 << 26); - rsize = 8; - break; - case 0x220: /* 0x220 - 0x227 */ - set |= (1 << 8); - rsize = 8; - break; - case 0x228: /* 0x228 - 0x22f */ - set |= (1 << 9); - rsize = 8; - break; - case 0x238: /* 0x238 - 0x23f */ - set |= (1 << 10); - rsize = 8; - break; - case 0x300: /* 0x300 -0x301 */ - set |= (1 << 18); - rsize = 2; - break; - case 0x400: - set_x |= (1 << 16); - rsize = 0x40; - break; - case 0x480: - set_x |= (1 << 17); - rsize = 0x40; - break; - case 0x500: - set_x |= (1 << 18); - rsize = 0x40; - break; - case 0x580: - set_x |= (1 << 19); - rsize = 0x40; - break; - case 0x4700: - set_x |= (1 << 22); - rsize = 0xc; - break; - case 0xfd60: - set_x |= (1 << 23); - rsize = 16; - break; - default: - rsize = 0; - /* try AGESA allocated region in region 0 */ - if ((var_num > 0) && ((base >= reg_var[0]) && - ((base + res->size) <= (reg_var[0] + reg_size[0])))) - rsize = reg_size[0]; - } - /* check if region found and matches the enable */ - if (res->size <= rsize) { - reg |= set; - reg_x |= set_x; - /* check if we can fit resource in variable range */ - } else if ((var_num < 3) && - ((res->size <= 16) || (res->size == 512))) { - /* use variable ranges if pre-defined do not match */ - switch (var_num) { - case 0: - reg_x |= (1 << 2); - if (res->size <= 16) { - wiosize |= (1 << 0); - } - break; - case 1: - reg_x |= (1 << 24); - if (res->size <= 16) - wiosize |= (1 << 2); - break; - case 2: - reg_x |= (1 << 25); - if (res->size <= 16) - wiosize |= (1 << 3); - break; - } - reg_var[var_num++] = - base & 0xffff; - } else { - printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n", - dev_path(child), base, end); - } - } - } - } - } - pci_write_config32(dev, 0x44, reg); - pci_write_config32(dev, 0x48, reg_x); - /* Set WideIO for as many IOs found (fall through is on purpose) */ - switch (var_num) { - case 3: - pci_write_config16(dev, 0x90, reg_var[2]); - __fallthrough; - case 2: - pci_write_config16(dev, 0x66, reg_var[1]); - __fallthrough; - case 1: - pci_write_config16(dev, 0x64, reg_var[0]); - break; - } - pci_write_config8(dev, 0x74, wiosize); -} - -static void hudson_lpc_enable_resources(struct device *dev) -{ - pci_dev_enable_resources(dev); - hudson_lpc_enable_childrens_resources(dev); -} - -static const char *lpc_acpi_name(const struct device *dev) -{ - if (dev->path.type != DEVICE_PATH_PCI) - return NULL; - - if (dev->path.pci.devfn == LPC_DEVFN) - return "LIBR"; - - return NULL; -} - -static void lpc_final(struct device *dev) -{ - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ - else - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - } -} - -static struct device_operations lpc_ops = { - .read_resources = hudson_lpc_read_resources, - .set_resources = hudson_lpc_set_resources, - .enable_resources = hudson_lpc_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_init, - .final = lpc_final, - .scan_bus = scan_static_bus, - .ops_pci = &pci_dev_ops_pci, - .acpi_name = lpc_acpi_name, -}; -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_LPC, -}; diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c deleted file mode 100644 index b99413c9c4..0000000000 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "hudson.h" -#include <southbridge/amd/common/amd_pci_util.h> -#include <bootstate.h> - -/* - * Update the PCI devices with a valid IRQ number - * that is set in the mainboard PCI_IRQ structures. - */ -static void set_pci_irqs(void *unused) -{ - /* Write PCI_INTR regs 0xC00/0xC01 */ - write_pci_int_table(); - - /* Write IRQs for all devicetree enabled devices */ - write_pci_cfg_irqs(); -} - -/* - * Hook this function into the PCI state machine - * on entry into BS_DEV_ENABLE. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pci_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_PCI, -}; diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h deleted file mode 100644 index d67395c9ee..0000000000 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _AGESA_HUDSON_PCI_DEVS_H_ -#define _AGESA_HUDSON_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define BUS0 0 - -/* XHCI */ -#define XHCI_DEV 0x10 -#define XHCI_FUNC 0 -#define XHCI_DEVID 0x7814 -#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) - -/* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7800 -#define AHCI_DEVID_MS 0x7801 -#define AHCI_DEVID_AMD 0x7804 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) - -/* OHCI */ -#define OHCI1_DEV 0x12 -#define OHCI1_FUNC 0 -#define OHCI2_DEV 0x13 -#define OHCI2_FUNC 0 -#define OHCI3_DEV 0x16 -#define OHCI3_FUNC 0 -#define OHCI4_DEV 0x14 -#define OHCI4_FUNC 5 -#define OHCI_DEVID 0x7807 -#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) -#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) -#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) -#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) - -/* EHCI */ -#define EHCI1_DEV 0x12 -#define EHCI1_FUNC 2 -#define EHCI2_DEV 0x13 -#define EHCI2_FUNC 2 -#define EHCI3_DEV 0x16 -#define EHCI3_FUNC 2 -#define EHCI_DEVID 0x7808 -#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) -#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) -#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) - -/* SMBUS */ -#define SMBUS_DEV 0x14 -#define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x780B -#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) - -/* IDE */ -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define IDE_DEV 0x14 -#define IDE_FUNC 1 -#define IDE_DEVID 0x780C -#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) -#endif - -/* HD Audio */ -#define HDA_DEV 0x14 -#define HDA_FUNC 2 -#define HDA_DEVID 0x780D -#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) - -/* LPC BUS */ -#define PCU_DEV 0x14 -#define LPC_DEV PCU_DEV -#define LPC_FUNC 3 -#define LPC_DEVID 0x780E -#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) - -/* PCI Ports */ -#define SB_PCI_PORT_DEV 0x14 -#define SB_PCI_PORT_FUNC 4 -#define SB_PCI_PORT_DEVID 0x780F -#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) - -/* SD Controller */ -#define SD_DEV 0x14 -#define SD_FUNC 7 -#define SD_DEVID 0x7806 -#define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) - -/* PCIe Ports */ -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_HUDSON) -#define SB_PCIE_DEV 0x15 -#define SB_PCIE_PORT1_FUNC 0 -#define SB_PCIE_PORT2_FUNC 1 -#define SB_PCIE_PORT3_FUNC 2 -#define SB_PCIE_PORT4_FUNC 3 -#define SB_PCIE_PORT1_DEVID 0x7820 -#define SB_PCIE_PORT2_DEVID 0x7821 -#define SB_PCIE_PORT3_DEVID 0x7822 -#define SB_PCIE_PORT4_DEVID 0x7823 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) -#endif - -#endif /* _AGESA_HUDSON_PCI_DEVS_H_ */ diff --git a/src/southbridge/amd/agesa/hudson/pcie.c b/src/southbridge/amd/agesa/hudson/pcie.c deleted file mode 100644 index 04827a44df..0000000000 --- a/src/southbridge/amd/agesa/hudson/pcie.c +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include "hudson.h" - -static void pcie_init(struct device *dev) -{ -} - -static struct pci_operations lops_pci = { - .set_subsystem = 0, -}; - -static struct device_operations pci_ops = { - .read_resources = pci_bus_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_bus_enable_resources, - .init = pcie_init, - .scan_bus = pci_scan_bridge, - .reset_bus = pci_bus_reset, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver pciea_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_PCIEA, -}; - -static const struct pci_driver pcieb_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_PCIEB, -}; -static const struct pci_driver pciec_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_PCIEC, -}; -static const struct pci_driver pcied_driver __pci_driver = { - .ops = &pci_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_PCIED, -}; diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c deleted file mode 100644 index 821fc39bcd..0000000000 --- a/src/southbridge/amd/agesa/hudson/ramtop.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/io.h> -#include <acpi/acpi.h> -#include "hudson.h" - -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - return (int)tmp; -} diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c deleted file mode 100644 index fbb62c88fc..0000000000 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <device/pci_ops.h> -#include <cf9_reset.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6c -#define HTIC_ColdR_Detect (1 << 4) -#define HTIC_BIOSR_Detect (1 << 5) -#define HTIC_INIT_Detect (1 << 6) - -void cf9_reset_prepare(void) -{ - u32 htic; - htic = pci_s_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_s_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); -} - -void do_board_reset(void) -{ - system_reset(); -} diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c deleted file mode 100644 index a742e22df9..0000000000 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <Proc/Fch/FchPlatform.h> -#include <Proc/Fch/Fch.h> -#include <device/device.h> -#include "hudson.h" -#include <AGESA.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> - -extern FCH_DATA_BLOCK InitEnvCfgDefault; -extern FCH_INTERFACE FchInterfaceDefault; -extern FCH_RESET_DATA_BLOCK InitResetCfgDefault; -extern FCH_RESET_INTERFACE FchResetInterfaceDefault; - -#define DUMP_FCH_SETTING 0 - -static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams) -{ - *FchParams = InitEnvCfgDefault; - - FchParams->Usb.Xhci0Enable = InitResetCfgDefault.FchReset.Xhci0Enable; - FchParams->Usb.Xhci1Enable = InitResetCfgDefault.FchReset.Xhci1Enable; - FchParams->Spi.SpiFastSpeed = InitResetCfgDefault.FastSpeed; - FchParams->Spi.WriteSpeed = InitResetCfgDefault.WriteSpeed; - FchParams->Spi.SpiMode = InitResetCfgDefault.Mode; - FchParams->Spi.AutoMode = InitResetCfgDefault.AutoMode; - FchParams->Spi.SpiBurstWrite = InitResetCfgDefault.BurstWrite; - FchParams->Sata.SataMode.Sata6AhciCap = (UINT8) InitResetCfgDefault.Sata6AhciCap; - FchParams->Misc.Cg2Pll = InitResetCfgDefault.Cg2Pll; - FchParams->Sata.SataMode.SataSetMaxGen2 = InitResetCfgDefault.SataSetMaxGen2; - FchParams->Sata.SataMode.SataClkMode = InitResetCfgDefault.SataClkMode; - FchParams->Sata.SataMode.SataModeReg = InitResetCfgDefault.SataModeReg; - FchParams->Sata.SataInternal100Spread = (UINT8) InitResetCfgDefault.SataInternal100Spread; - FchParams->Spi.SpiSpeed = InitResetCfgDefault.SpiSpeed; - FchParams->Gpp = InitResetCfgDefault.Gpp; - FchParams->Gpp.GppFunctionEnable = FchResetInterfaceDefault.GppEnable; - - FchParams->Gpp.GppLinkConfig = UserOptions.FchBldCfg->CfgFchGppLinkConfig; - FchParams->Gpp.PortCfg[0].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort0Present; - FchParams->Gpp.PortCfg[1].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort1Present; - FchParams->Gpp.PortCfg[2].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort2Present; - FchParams->Gpp.PortCfg[3].PortPresent = UserOptions.FchBldCfg->CfgFchGppPort3Present; - FchParams->Gpp.PortCfg[0].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort0HotPlug; - FchParams->Gpp.PortCfg[1].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort1HotPlug; - FchParams->Gpp.PortCfg[2].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort2HotPlug; - FchParams->Gpp.PortCfg[3].PortHotPlug = UserOptions.FchBldCfg->CfgFchGppPort3HotPlug; - - FchParams->HwAcpi.Smbus0BaseAddress = UserOptions.FchBldCfg->CfgSmbus0BaseAddress; - FchParams->HwAcpi.Smbus1BaseAddress = UserOptions.FchBldCfg->CfgSmbus1BaseAddress; - FchParams->HwAcpi.SioPmeBaseAddress = UserOptions.FchBldCfg->CfgSioPmeBaseAddress; - FchParams->HwAcpi.AcpiPm1EvtBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1EvtBlkAddr; - FchParams->HwAcpi.AcpiPm1CntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPm1CntBlkAddr; - FchParams->HwAcpi.AcpiPmTmrBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmTmrBlkAddr; - FchParams->HwAcpi.CpuControlBlkAddr = UserOptions.FchBldCfg->CfgCpuControlBlkAddr; - FchParams->HwAcpi.AcpiGpe0BlkAddr = UserOptions.FchBldCfg->CfgAcpiGpe0BlkAddr; - FchParams->HwAcpi.SmiCmdPortAddr = UserOptions.FchBldCfg->CfgSmiCmdPortAddr; - FchParams->HwAcpi.AcpiPmaCntBlkAddr = UserOptions.FchBldCfg->CfgAcpiPmaCntBlkAddr; - FchParams->HwAcpi.WatchDogTimerBase = UserOptions.FchBldCfg->CfgWatchDogTimerBase; - FchParams->Sata.SataRaid5Ssid = UserOptions.FchBldCfg->CfgSataRaid5Ssid; - FchParams->Sata.SataRaidSsid = UserOptions.FchBldCfg->CfgSataRaidSsid; - FchParams->Sata.SataAhciSsid = UserOptions.FchBldCfg->CfgSataAhciSsid; - FchParams->Sata.SataIdeSsid = UserOptions.FchBldCfg->CfgSataIdeSsid; - FchParams->Spi.RomBaseAddress = UserOptions.FchBldCfg->CfgSpiRomBaseAddress; - FchParams->Sd.SdSsid = UserOptions.FchBldCfg->CfgSdSsid; - FchParams->Spi.LpcSsid = UserOptions.FchBldCfg->CfgLpcSsid; - FchParams->Hpet.HpetBase = UserOptions.FchBldCfg->CfgHpetBaseAddress; - FchParams->Azalia.AzaliaSsid = UserOptions.FchBldCfg->CfgAzaliaSsid; - FchParams->Smbus.SmbusSsid = UserOptions.FchBldCfg->CfgSmbusSsid; - FchParams->Ide.IdeSsid = UserOptions.FchBldCfg->CfgIdeSsid; - FchParams->Usb.EhciSsid = UserOptions.FchBldCfg->CfgEhciSsid; - FchParams->Usb.OhciSsid = UserOptions.FchBldCfg->CfgOhciSsid; - FchParams->Usb.XhciSsid = UserOptions.FchBldCfg->CfgXhciSsid; - FchParams->Ir.IrPinControl = UserOptions.FchBldCfg->CfgFchIrPinControl; - FchParams->Sd.SdClockControl = UserOptions.FchBldCfg->CfgFchSdClockControl; - - FchParams->Sd.SdConfig = FchInterfaceDefault.SdConfig; - FchParams->Azalia.AzaliaEnable = FchInterfaceDefault.AzaliaController; - FchParams->Ir.IrConfig = FchInterfaceDefault.IrConfig; - FchParams->Ab.NbSbGen2 = FchInterfaceDefault.UmiGen2; - FchParams->Sata.SataClass = FchInterfaceDefault.SataClass; - FchParams->Sata.SataMode.SataEnable = FchInterfaceDefault.SataEnable; - FchParams->Sata.SataMode.IdeEnable = FchInterfaceDefault.IdeEnable; - FchParams->Sata.SataIdeMode = FchInterfaceDefault.SataIdeMode; - FchParams->Usb.Ohci1Enable = FchInterfaceDefault.Ohci1Enable; - FchParams->Usb.Ehci1Enable = FchInterfaceDefault.Ohci1Enable; - FchParams->Usb.Ohci2Enable = FchInterfaceDefault.Ohci2Enable; - FchParams->Usb.Ehci2Enable = FchInterfaceDefault.Ohci2Enable; - FchParams->Usb.Ohci3Enable = FchInterfaceDefault.Ohci3Enable; - FchParams->Usb.Ehci3Enable = FchInterfaceDefault.Ohci3Enable; - FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; - FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; - - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; - -#if DUMP_FCH_SETTING - int i; - - for (i = 0; i < sizeof(FchParams); i++) { - printk(BIOS_DEBUG, " %02x", ((u8 *)FchParams)[i]); - if ((i % 16) == 15) - printk(BIOS_DEBUG, "\n"); - } -#endif -} - -AGESA_STATUS fchs3earlyrestore(AMD_CONFIG_PARAMS *StdHeader) -{ - FCH_DATA_BLOCK FchParams; - - /* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */ - s3_resume_init_data(&FchParams); - - FchParams.StdHeader = StdHeader; - FchInitS3EarlyRestore(&FchParams); - return AGESA_SUCCESS; -} - -AGESA_STATUS fchs3laterestore(AMD_CONFIG_PARAMS *StdHeader) -{ - FCH_DATA_BLOCK FchParams; - - /* FIXME: Recover FCH_DATA_BLOCK from CBMEM. */ - s3_resume_init_data(&FchParams); - - FchParams.StdHeader = StdHeader; - FchInitS3LateRestore(&FchParams); - - return AGESA_SUCCESS; -} diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c deleted file mode 100644 index f04dd5980c..0000000000 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - -#include "hudson.h" - -static void sata_init(struct device *dev) -{ -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - /************************************** - * Configure the SATA port multiplier * - **************************************/ - #define BYTE_TO_DWORD_OFFSET(x) (x / 4) - #define AHCI_BASE_ADDRESS_REG 0x24 - #define MISC_CONTROL_REG 0x40 - #define UNLOCK_BIT (1 << 0) - #define SATA_CAPABILITIES_REG 0xFC - #define CFG_CAP_SPM (1 << 12) - - volatile u32 *ahci_ptr = - (u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); - u32 temp; - - /* unlock the write-protect */ - temp = pci_read_config32(dev, MISC_CONTROL_REG); - temp |= UNLOCK_BIT; - pci_write_config32(dev, MISC_CONTROL_REG, temp); - - /* set the SATA AHCI mode to allow port expanders */ - *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM; - - /* lock the write-protect */ - temp = pci_read_config32(dev, MISC_CONTROL_REG); - temp &= ~UNLOCK_BIT; - pci_write_config32(dev, MISC_CONTROL_REG, temp); -#endif -}; - -static struct pci_operations lops_pci = { - /* .set_subsystem = pci_dev_set_subsystem, */ -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .ops_pci = &lops_pci, -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_SATA, -}; - -static const struct pci_driver sata0_driver_ahci __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_SATA_AHCI, -}; diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c deleted file mode 100644 index f3ea0a5eb4..0000000000 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> - -#include "chip.h" -#include "hudson.h" - -static void sd_init(struct device *dev) -{ - struct southbridge_amd_agesa_hudson_config *sd_chip = dev->chip_info; - u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); - u8 sd_mode = 0; - - if (sd_chip) - sd_mode = sd_chip->sd_mode; - - if (sd_mode == 3) { /* SD 3.0 mode */ - pci_write_config32(dev, 0xA4, 0x31FEC8B2); - pci_write_config32(dev, 0xA8, 0x00002503); - pci_write_config32(dev, 0xB0, 0x02180C19); - pci_write_config32(dev, 0xD0, 0x0000078B); - } - else { /* SD 2.0 mode */ - if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */ - pci_write_config32(dev, 0xA4, 0x31DE32B2); - pci_write_config32(dev, 0xB0, 0x01180C19); - pci_write_config32(dev, 0xD0, 0x0000058B); - } - else { /* Stepping >= A1 */ - pci_write_config32(dev, 0xA4, 0x31FE3FB2); - pci_write_config32(dev, 0xB0, 0x01180C19); - pci_write_config32(dev, 0xD0, 0x0000078B); - } - } -} - -static struct device_operations sd_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sd_init, -}; - -static const struct pci_driver sd_driver __pci_driver = { - .ops = &sd_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_YANGTZE_SD, -}; diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c deleted file mode 100644 index 8fd124a5a3..0000000000 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/smbus.h> -#include <arch/ioapic.h> - -#include "hudson.h" -#include "smbus.c" - -#define NMI_OFF 0 - -#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -/* -* HUDSON enables all USB controllers by default in SMBUS Control. -* HUDSON enables SATA by default in SMBUS Control. -*/ - -static void sm_init(struct device *dev) -{ - setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); -} - -static int lsmbus_recv_byte(struct device *dev) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_recv_byte(res->base, device); -} - -static int lsmbus_send_byte(struct device *dev, u8 val) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_send_byte(res->base, device, val); -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - u32 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - - res = find_resource(pbus->dev, 0x90); - - return do_smbus_write_byte(res->base, device, address, val); -} -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static void hudson_sm_read_resources(struct device *dev) -{ -} - -static void hudson_sm_set_resources(struct device *dev) -{ -} - -static struct device_operations smbus_ops = { - .read_resources = hudson_sm_read_resources, - .set_resources = hudson_sm_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sm_init, - .scan_bus = scan_smbus, - .ops_pci = &pci_dev_ops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_SM, -}; diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c deleted file mode 100644 index 43f8ca75d3..0000000000 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ /dev/null @@ -1,232 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _HUDSON_SMBUS_C_ -#define _HUDSON_SMBUS_C_ - -#include <arch/io.h> -#include <stdint.h> -#include "smbus.h" - -static int smbus_wait_until_ready(u32 smbus_io_base) -{ - u32 loops; - - loops = SMBUS_TIMEOUT; - do { - u8 val; - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { /* ready now */ - return 0; - } - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - - return -2; /* time out */ -} - -static int smbus_wait_until_done(u32 smbus_io_base) -{ - u32 loops; - - loops = SMBUS_TIMEOUT; - do { - u8 val; - - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) { - return -5; /* error */ - } - if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ - return 0; - } - } while (--loops); - - return -3; /* timeout */ -} - -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - return byte; -} - -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - return 0; -} - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - return byte; -} - -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - return -2; /* not ready */ - } - - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - return 0; -} - -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} - -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} - -/* space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) -{ - u32 tmp; - - /* read axindc to tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} -#endif diff --git a/src/southbridge/amd/agesa/hudson/smbus.h b/src/southbridge/amd/agesa/hudson/smbus.h deleted file mode 100644 index ecee071462..0000000000 --- a/src/southbridge/amd/agesa/hudson/smbus.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef HUDSON_SMBUS_H -#define HUDSON_SMBUS_H - -#include <stdint.h> - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 - -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc - -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 - -#define AB_INDX 0xcd8 -#define AB_DATA (AB_INDX + 4) - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - -#define abcfg_reg(reg, mask, val) \ - alink_ab_indx((ABCFG), (reg), (mask), (val)) -#define axcfg_reg(reg, mask, val) \ - alink_ab_indx((AXCFG), (reg), (mask), (val)) -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXC), (reg), (mask), (val)) -#define axindxp_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXP), (reg), (mask), (val)) -#define rcindxc_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) -#define rcindxp_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); - -#endif diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c deleted file mode 100644 index c240e5b877..0000000000 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <device/pci_def.h> -#include <device/device.h> -#include <console/console.h> -#include <stddef.h> -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <Porting.h> -#include <AGESA.h> -#include <amdlib.h> -#include <northbridge/amd/agesa/dimmSpd.h> - -/*----------------------------------------------------------------------------- - * - * readSmbusByteData - read a single SPD byte from any offset - */ - -static int readSmbusByteData(int iobase, int address, char *buffer, int offset) -{ - unsigned int status; - UINT64 limit; - - address |= 1; // set read bit - - __outbyte(iobase + 0, 0xFF); // clear error status - __outbyte(iobase + 1, 0x1F); // clear error status - __outbyte(iobase + 3, offset); // offset in eeprom - __outbyte(iobase + 4, address); // slave address and read bit - __outbyte(iobase + 2, 0x48); // read byte command - - // time limit to avoid hanging for unexpected error status (should never happen) - limit = __rdtsc() + 2000000000 / 10; - for (;;) - { - status = __inbyte(iobase); - if (__rdtsc() > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte(iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*----------------------------------------------------------------------------- - * - * readSmbusByte - read a single SPD byte from the default offset - * this function is faster function readSmbusByteData - */ - -static int readSmbusByte(int iobase, int address, char *buffer) -{ - unsigned int status; - UINT64 limit; - - __outbyte(iobase + 0, 0xFF); // clear error status - __outbyte(iobase + 2, 0x44); // read command - - // time limit to avoid hanging for unexpected error status - limit = __rdtsc() + 2000000000 / 10; - for (;;) - { - status = __inbyte(iobase); - if (__rdtsc() > limit) break; - if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting - if ((status & 1) == 1) continue; // HostBusy set, keep waiting - break; - } - - buffer [0] = __inbyte(iobase + 5); - if (status == 2) status = 0; // check for done with no errors - return status; -} - -/*--------------------------------------------------------------------------- - * - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ - -static int readspd(int iobase, int SmbusSlaveAddress, char *buffer, int count) -{ - int index, error; - - printk(BIOS_SPEW, "-------------READING SPD-----------\n"); - printk(BIOS_SPEW, "iobase: 0x%08X, SmbusSlave: 0x%08X, count: %d\n", - iobase, SmbusSlaveAddress, count); - - /* read the first byte using offset zero */ - error = readSmbusByteData(iobase, SmbusSlaveAddress, buffer, 0); - - if (error) { - printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); - return error; - } - - /* read the remaining bytes using auto-increment for speed */ - for (index = 1; index < count; index++) - { - error = readSmbusByte(iobase, SmbusSlaveAddress, &buffer [index]); - if (error) { - printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); - return error; - } - } - printk(BIOS_SPEW, "\n"); - printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n"); - - return 0; -} - -static void setupFch(int ioBase) -{ - pm_write16(0x2c, ioBase | 1); - __outbyte(ioBase + 0x0E, 66000000 / 400000 / 4); // set SMBus clock to 400 KHz -} - -int hudson_readSpd(int spdAddress, char *buf, size_t len) -{ - int ioBase = 0xB00; - setupFch(ioBase); - return readspd(ioBase, spdAddress, buf, len); -} diff --git a/src/southbridge/amd/agesa/hudson/smi.c b/src/southbridge/amd/agesa/hudson/smi.c deleted file mode 100644 index 560b66679b..0000000000 --- a/src/southbridge/amd/agesa/hudson/smi.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Utilities for SMM setup - */ - -#include <amdblocks/acpimmio.h> -#include <cpu/x86/smm.h> - -#include "smi.h" - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h deleted file mode 100644 index d0187b8c16..0000000000 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Utilities for SMI handlers and SMM setup - */ - -#ifndef _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H -#define _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H - -#include <device/mmio.h> - -/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. - * This is defined by AGESA, but we dpn't include AGESA headers to avoid - * polluting the namesace. - */ -#define SMI_BASE 0xfed80200 - -#define SMI_REG_SMITRIG0 0x98 -#define SMITRG0_EOS (1 << 28) -#define SMITRG0_SMIENB (1 << 31) - -#define SMI_REG_CONTROL0 0xa0 - -enum smi_mode { - SMI_MODE_DISABLE = 0, - SMI_MODE_SMI = 1, - SMI_MODE_NMI = 2, - SMI_MODE_IRQ13 = 3, -}; - -enum smi_lvl { - SMI_LVL_LOW = 0, - SMI_LVL_HIGH = 1, -}; - -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); -void hudson_disable_gevent_smi(uint8_t gevent); -void hudson_enable_acpi_cmd_smi(void); - -#endif /* _SOUTHBRIDGE_AMD_AGESA_HUDSON_SMI_H */ diff --git a/src/southbridge/amd/agesa/hudson/smi_util.c b/src/southbridge/amd/agesa/hudson/smi_util.c deleted file mode 100644 index 3dc2d8a31e..0000000000 --- a/src/southbridge/amd/agesa/hudson/smi_util.c +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * SMM utilities used in both SMM and normal mode - */ - -#include <amdblocks/acpimmio.h> -#include <console/console.h> - -#include "smi.h" - -#define HUDSON_SMI_ACPI_COMMAND 75 - -static void configure_smi(uint8_t smi_num, uint8_t mode) -{ - uint8_t reg32_offset, bit_offset; - uint32_t reg32; - - /* SMI sources range from [0:149] */ - if (smi_num > 149) { - printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); - return; - } - - /* 16 sources per register, 2 bits per source; registers are 4 bytes */ - reg32_offset = (smi_num / 16) * 4; - bit_offset = (smi_num % 16) * 2; - - reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); - reg32 &= ~(0x3 << (bit_offset)); - reg32 |= (mode & 0x3) << bit_offset; - smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); -} - -/** - * Configure generation of interrupts for given GEVENT pin - * - * @param gevent The GEVENT pin number. Valid values are 0 thru 23 - * @param mode The type of event this pin should generate. Note that only - * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. - * @param level SMI_LVL_LOW or SMI_LVL_HIGH - */ -void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) -{ - uint32_t reg32; - /* GEVENT pins range from [0:23] */ - if (gevent > 23) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - configure_smi(gevent, mode); - - /* And set the trigger level */ - reg32 = smi_read32(SMI_REG_SMITRIG0); - reg32 &= ~(1 << gevent); - reg32 |= (level & 0x1) << gevent; - smi_write32(SMI_REG_SMITRIG0, reg32); -} - -/** Disable events from given GEVENT pin */ -void hudson_disable_gevent_smi(uint8_t gevent) -{ - /* GEVENT pins range from [0:23] */ - if (gevent > 23) { - printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); - return; - } - - /* SMI0 source is GEVENT0 and so on */ - configure_smi(gevent, SMI_MODE_DISABLE); -} - -/** Enable SMIs on writes to ACPI SMI command port */ -void hudson_enable_acpi_cmd_smi(void) -{ - configure_smi(HUDSON_SMI_ACPI_COMMAND, SMI_MODE_SMI); -} diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c deleted file mode 100644 index a942c24ada..0000000000 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * SMI handler for Hudson southbridges - */ - -#include <amdblocks/acpimmio.h> -#include <arch/io.h> -#include <cpu/x86/smm.h> - -#include "hudson.h" -#include "smi.h" - -#define SMI_0x88_ACPI_COMMAND (1 << 11) - -enum smi_source { - SMI_SOURCE_SCI = (1 << 0), - SMI_SOURCE_GPE = (1 << 1), - SMI_SOURCE_0x84 = (1 << 2), - SMI_SOURCE_0x88 = (1 << 3), - SMI_SOURCE_IRQ_TRAP = (1 << 4), - SMI_SOURCE_0x90 = (1 << 5) -}; - -static void hudson_apmc_smi_handler(void) -{ - u32 reg32; - const uint8_t cmd = inb(ACPI_SMI_CTL_PORT); - - switch (cmd) { - case ACPI_SMI_CMD_ENABLE: - reg32 = inl(ACPI_PM1_CNT_BLK); - reg32 |= (1 << 0); /* SCI_EN */ - outl(reg32, ACPI_PM1_CNT_BLK); - break; - case ACPI_SMI_CMD_DISABLE: - reg32 = inl(ACPI_PM1_CNT_BLK); - reg32 &= ~(1 << 0); /* clear SCI_EN */ - outl(ACPI_PM1_CNT_BLK, reg32); - break; - } - - mainboard_smi_apmc(cmd); -} - -int southbridge_io_trap_handler(int smif) -{ - return 0; -} - -static void process_smi_sci(void) -{ - const uint32_t status = smi_read32(0x10); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x10, status); -} - -static void process_gpe_smi(void) -{ - const uint32_t status = smi_read32(0x80); - const uint32_t gevent_mask = (1 << 24) - 1; - - /* Only Bits [23:0] indicate GEVENT SMIs. */ - if (status & gevent_mask) { - /* A GEVENT SMI occurred */ - mainboard_smi_gpi(status & gevent_mask); - } - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x80, status); -} - -static void process_smi_0x84(void) -{ - const uint32_t status = smi_read32(0x84); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x84, status); -} - -static void process_smi_0x88(void) -{ - const uint32_t status = smi_read32(0x88); - - if (status & SMI_0x88_ACPI_COMMAND) { - /* Command received via ACPI SMI command port */ - hudson_apmc_smi_handler(); - } - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x88, status); -} - -static void process_smi_0x8c(void) -{ - const uint32_t status = smi_read32(0x8c); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x8c, status); -} - -static void process_smi_0x90(void) -{ - const uint32_t status = smi_read32(0x90); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x90, status); -} - -void southbridge_smi_handler(void) -{ - const uint16_t smi_src = smi_read16(0x94); - - if (smi_src & SMI_SOURCE_SCI) - process_smi_sci(); - if (smi_src & SMI_SOURCE_GPE) - process_gpe_smi(); - if (smi_src & SMI_SOURCE_0x84) - process_smi_0x84(); - if (smi_src & SMI_SOURCE_0x88) - process_smi_0x88(); - if (smi_src & SMI_SOURCE_IRQ_TRAP) - process_smi_0x8c(); - if (smi_src & SMI_SOURCE_0x90) - process_smi_0x90(); -} - -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); -} diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c deleted file mode 100644 index 986f094a77..0000000000 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ /dev/null @@ -1,170 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <device/mmio.h> -#include <console/console.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <stddef.h> - -#include <Proc/Fch/FchPlatform.h> - -#define SPI_REG_OPCODE 0x0 -#define SPI_REG_CNTRL01 0x1 -#define SPI_REG_CNTRL02 0x2 - #define CNTRL02_FIFO_RESET (1 << 4) - #define CNTRL02_EXEC_OPCODE (1 << 0) -#define SPI_REG_CNTRL03 0x3 - #define CNTRL03_SPIBUSY (1 << 7) -#define SPI_REG_FIFO 0xc -#define SPI_REG_CNTRL11 0xd - #define CNTRL11_FIFOPTR_MASK 0x07 - -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) -#define AMD_SB_SPI_TX_LEN 64 -#else -#define AMD_SB_SPI_TX_LEN 8 -#endif - -static uintptr_t spibar; - -static inline uint8_t spi_read(uint8_t reg) -{ - return read8((void *)(spibar + reg)); -} - -static inline void spi_write(uint8_t reg, uint8_t val) -{ - write8((void *)(spibar + reg), val); -} - -static void reset_internal_fifo_pointer(void) -{ - uint8_t reg8; - - do { - reg8 = spi_read(SPI_REG_CNTRL02); - reg8 |= CNTRL02_FIFO_RESET; - spi_write(SPI_REG_CNTRL02, reg8); - } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK); -} - -static void execute_command(void) -{ - uint8_t reg8; - - reg8 = spi_read(SPI_REG_CNTRL02); - reg8 |= CNTRL02_EXEC_OPCODE; - spi_write(SPI_REG_CNTRL02, reg8); - - while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && - (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY)); -} - -void spi_init(void) -{ - struct device *dev; - - dev = pcidev_on_root(0x14, 3); - spibar = pci_read_config32(dev, 0xA0) & ~0x1F; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - /* First byte is cmd which can not be sent through FIFO. */ - u8 cmd = *(u8 *)dout++; - u8 readoffby1; - size_t count; - - bytesout--; - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (bytesout > AMD_SB_SPI_TX_LEN) { - printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - readoffby1 = bytesout ? 0 : 1; - - if (CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)) { - spi_write(0x1E, 5); - spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ - spi_write(0x1E, 6); - spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ - } else { - u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; - spi_write(SPI_REG_CNTRL01, readwrite); - } - spi_write(SPI_REG_OPCODE, cmd); - - reset_internal_fifo_pointer(); - for (count = 0; count < bytesout; count++, dout++) { - spi_write(SPI_REG_FIFO, *(uint8_t *)dout); - } - - reset_internal_fifo_pointer(); - execute_command(); - - reset_internal_fifo_pointer(); - /* Skip the bytes we sent. */ - for (count = 0; count < bytesout; count++) { - spi_read(SPI_REG_FIFO); - } - - for (count = 0; count < bytesin; count++, din++) { - *(uint8_t *)din = spi_read(SPI_REG_FIFO); - } - - return 0; -} - -int chipset_volatile_group_begin(const struct spi_flash *flash) -{ - if (!CONFIG(HUDSON_IMC_FWM)) - return 0; - - ImcSleep(NULL); - return 0; -} - -int chipset_volatile_group_end(const struct spi_flash *flash) -{ - if (!CONFIG(HUDSON_IMC_FWM)) - return 0; - - ImcWakeup(NULL); - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = AMD_SB_SPI_TX_LEN, - .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c deleted file mode 100644 index 694f2bfd77..0000000000 --- a/src/southbridge/amd/agesa/hudson/usb.c +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ehci.h> -#include "hudson.h" - -static void usb_init(struct device *dev) -{ -} - -static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = usb_init, - .ops_pci = &pci_dev_ops_pci, -}; - -static const struct pci_driver usb_0_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_USB_18_0, -}; - -static const struct pci_driver usb_1_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_USB_18_2, -}; - -static const struct pci_driver usb_4_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VID_AMD, - .device = PCI_DID_AMD_SB900_USB_20_5, -}; diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig deleted file mode 100644 index 59444f171f..0000000000 --- a/src/southbridge/amd/cimx/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config AMD_SB_CIMX - bool - default n - -source "src/southbridge/amd/cimx/sb800/Kconfig" diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc deleted file mode 100644 index f814729753..0000000000 --- a/src/southbridge/amd/cimx/Makefile.inc +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h deleted file mode 100644 index c6ba09f282..0000000000 --- a/src/southbridge/amd/cimx/sb800/Amd.h +++ /dev/null @@ -1,352 +0,0 @@ -/***************************************************************************** - * AMD Generic Encapsulated Software Architecture */ -/** - * @file - * - * Agesa structures and definitions - * - * Contains AMD AGESA/CIMx core interface - * - */ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _AMD_H_ -#define _AMD_H_ - -// AGESA Types and Definitions -#ifndef NULL - #define NULL 0 -#endif - -#define LAST_ENTRY 0xFFFFFFFF -#define IOCF8 0xCF8 -#define IOCFC 0xCFC -#define IN -#define OUT - -#ifndef Int16FromChar -#define Int16FromChar(a, b) ((a) << 0 | (b) << 8) -#endif -#ifndef Int32FromChar -#define Int32FromChar(a, b, c, d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24) -#endif - -#define IMAGE_SIGNATURE Int32FromChar('$', 'A', 'M', 'D') - -typedef unsigned int AGESA_STATUS; - -#define AGESA_SUCCESS ((AGESA_STATUS) 0x0) -#define AGESA_ALERT ((AGESA_STATUS) 0x40000000) -#define AGESA_WARNING ((AGESA_STATUS) 0x40000001) -#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003) -#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001) -#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002) -#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003) - -typedef AGESA_STATUS(*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, - void *ConfigPtr); -typedef AGESA_STATUS(*IMAGE_ENTRY) (IN OUT void *ConfigPtr); -typedef AGESA_STATUS(*MODULE_ENTRY) (IN OUT void *ConfigPtr); - -///This allocation type is used by the AmdCreateStruct entry point -typedef enum { - PreMemHeap = 0, ///< Create heap in cache. - PostMemDram, ///< Create heap in memory. - ByHost ///< Create heap by Host. -} ALLOCATION_METHOD; - -/// These width descriptors are used by the library function, and others, to specify the data size -typedef enum ACCESS_WIDTH { - AccessWidth8 = 1, ///< Access width is 8 bits. - AccessWidth16, ///< Access width is 16 bits. - AccessWidth32, ///< Access width is 32 bits. - AccessWidth64, ///< Access width is 64 bits. - - AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data. - AccessS3SaveWidth16, ///< Save 16 bits data. - AccessS3SaveWidth32, ///< Save 32 bits data. - AccessS3SaveWidth64, ///< Save 64 bits data. -} ACCESS_WIDTH; - -// AGESA Structures - -/// The standard header for all AGESA services. -typedef struct _AMD_CONFIG_PARAMS { - IN unsigned int ImageBasePtr; ///< The AGESA Image base address. - IN unsigned int Func; ///< The service desired, @sa dispatch.h. - IN unsigned int AltImageBasePtr; ///< Alternate Image location - IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured. - union { ///< Callback pointer - IN unsigned long long PlaceHolder; ///< Place holder - IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA - } CALLBACK; - IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use. -} AMD_CONFIG_PARAMS; - -/// AGESA Binary module header structure -typedef struct _AMD_IMAGE_HEADER { - IN unsigned int Signature; ///< Binary Signature - IN signed char CreatorID[8]; ///< 8 characters ID - IN signed char Version[12]; ///< 12 characters version - IN unsigned int ModuleInfoOffset; ///< Offset of module - IN unsigned int EntryPointAddress; ///< Entry address - IN unsigned int ImageBase; ///< Image base - IN unsigned int RelocTableOffset; ///< Relocate Table offset - IN unsigned int ImageSize; ///< Size - IN unsigned short Checksum; ///< Checksum - IN unsigned char ImageType; ///< Type - IN unsigned char V_Reserved; ///< Reserved -} AMD_IMAGE_HEADER; - -/// AGESA Binary module header structure -typedef struct _AMD_MODULE_HEADER { - IN unsigned int ModuleHeaderSignature; ///< Module signature - IN signed char ModuleIdentifier[8]; ///< 8 characters ID - IN signed char ModuleVersion[12]; ///< 12 characters version - IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher - IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link -} AMD_MODULE_HEADER; - -#define FUNC_0 0 // bit-placed for PCI address creation -#define FUNC_1 1 -#define FUNC_2 2 -#define FUNC_3 3 -#define FUNC_4 4 -#define FUNC_5 5 -#define FUNC_6 6 -#define FUNC_7 7 - -// SBDFO - Segment Bus Device Function Offset -// 31:28 Segment (4-bits) -// 27:20 Bus (8-bits) -// 19:15 Device (5-bits) -// 14:12 Function (3-bits) -// 11:00 Offset (12-bits) - -#define ILLEGAL_SBDFO 0xFFFFFFFF - -/// CPUID data received registers format -typedef struct _CPUID_DATA { - IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX - IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX - IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX - IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX -} CPUID_DATA; - -#define WARM_RESET 1 -#define COLD_RESET 2 // Cold reset -#define RESET_CPU 4 // Triggers a CPU reset - -/// HT frequency for external callbacks -typedef enum { - HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks - HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks - HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks - HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks - HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks - HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks - HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks - HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks - HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks - HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks - HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks - HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks - HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks - HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks - HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks - HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks -} HT_FREQUENCIES; - -#ifndef BIT0 - #define BIT0 0x0000000000000001ull -#endif -#ifndef BIT1 - #define BIT1 0x0000000000000002ull -#endif -#ifndef BIT2 - #define BIT2 0x0000000000000004ull -#endif -#ifndef BIT3 - #define BIT3 0x0000000000000008ull -#endif -#ifndef BIT4 - #define BIT4 0x0000000000000010ull -#endif -#ifndef BIT5 - #define BIT5 0x0000000000000020ull -#endif -#ifndef BIT6 - #define BIT6 0x0000000000000040ull -#endif -#ifndef BIT7 - #define BIT7 0x0000000000000080ull -#endif -#ifndef BIT8 - #define BIT8 0x0000000000000100ull -#endif -#ifndef BIT9 - #define BIT9 0x0000000000000200ull -#endif -#ifndef BIT10 - #define BIT10 0x0000000000000400ull -#endif -#ifndef BIT11 - #define BIT11 0x0000000000000800ull -#endif -#ifndef BIT12 - #define BIT12 0x0000000000001000ull -#endif -#ifndef BIT13 - #define BIT13 0x0000000000002000ull -#endif -#ifndef BIT14 - #define BIT14 0x0000000000004000ull -#endif -#ifndef BIT15 - #define BIT15 0x0000000000008000ull -#endif -#ifndef BIT16 - #define BIT16 0x0000000000010000ull -#endif -#ifndef BIT17 - #define BIT17 0x0000000000020000ull -#endif -#ifndef BIT18 - #define BIT18 0x0000000000040000ull -#endif -#ifndef BIT19 - #define BIT19 0x0000000000080000ull -#endif -#ifndef BIT20 - #define BIT20 0x0000000000100000ull -#endif -#ifndef BIT21 - #define BIT21 0x0000000000200000ull -#endif -#ifndef BIT22 - #define BIT22 0x0000000000400000ull -#endif -#ifndef BIT23 - #define BIT23 0x0000000000800000ull -#endif -#ifndef BIT24 - #define BIT24 0x0000000001000000ull -#endif -#ifndef BIT25 - #define BIT25 0x0000000002000000ull -#endif -#ifndef BIT26 - #define BIT26 0x0000000004000000ull -#endif -#ifndef BIT27 - #define BIT27 0x0000000008000000ull -#endif -#ifndef BIT28 - #define BIT28 0x0000000010000000ull -#endif -#ifndef BIT29 - #define BIT29 0x0000000020000000ull -#endif -#ifndef BIT30 - #define BIT30 0x0000000040000000ull -#endif -#ifndef BIT31 - #define BIT31 0x0000000080000000ull -#endif -#ifndef BIT32 - #define BIT32 0x0000000100000000ull -#endif -#ifndef BIT33 - #define BIT33 0x0000000200000000ull -#endif -#ifndef BIT34 - #define BIT34 0x0000000400000000ull -#endif -#ifndef BIT35 - #define BIT35 0x0000000800000000ull -#endif -#ifndef BIT36 - #define BIT36 0x0000001000000000ull -#endif -#ifndef BIT37 - #define BIT37 0x0000002000000000ull -#endif -#ifndef BIT38 - #define BIT38 0x0000004000000000ull -#endif -#ifndef BIT39 - #define BIT39 0x0000008000000000ull -#endif -#ifndef BIT40 - #define BIT40 0x0000010000000000ull -#endif -#ifndef BIT41 - #define BIT41 0x0000020000000000ull -#endif -#ifndef BIT42 - #define BIT42 0x0000040000000000ull -#endif -#ifndef BIT43 - #define BIT43 0x0000080000000000ull -#endif -#ifndef BIT44 - #define BIT44 0x0000100000000000ull -#endif -#ifndef BIT45 - #define BIT45 0x0000200000000000ull -#endif -#ifndef BIT46 - #define BIT46 0x0000400000000000ull -#endif -#ifndef BIT47 - #define BIT47 0x0000800000000000ull -#endif -#ifndef BIT48 - #define BIT48 0x0001000000000000ull -#endif -#ifndef BIT49 - #define BIT49 0x0002000000000000ull -#endif -#ifndef BIT50 - #define BIT50 0x0004000000000000ull -#endif -#ifndef BIT51 - #define BIT51 0x0008000000000000ull -#endif -#ifndef BIT52 - #define BIT52 0x0010000000000000ull -#endif -#ifndef BIT53 - #define BIT53 0x0020000000000000ull -#endif -#ifndef BIT54 - #define BIT54 0x0040000000000000ull -#endif -#ifndef BIT55 - #define BIT55 0x0080000000000000ull -#endif -#ifndef BIT56 - #define BIT56 0x0100000000000000ull -#endif -#ifndef BIT57 - #define BIT57 0x0200000000000000ull -#endif -#ifndef BIT58 - #define BIT58 0x0400000000000000ull -#endif -#ifndef BIT59 - #define BIT59 0x0800000000000000ull -#endif -#ifndef BIT60 - #define BIT60 0x1000000000000000ull -#endif -#ifndef BIT61 - #define BIT61 0x2000000000000000ull -#endif -#ifndef BIT62 - #define BIT62 0x4000000000000000ull -#endif -#ifndef BIT63 - #define BIT63 0x8000000000000000ull -#endif -#endif diff --git a/src/southbridge/amd/cimx/sb800/AmdSbLib.h b/src/southbridge/amd/cimx/sb800/AmdSbLib.h deleted file mode 100644 index 70c0b3e213..0000000000 --- a/src/southbridge/amd/cimx/sb800/AmdSbLib.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _AMD_SB_LIB_H_ -#define _AMD_SB_LIB_H_ - -#include <console/vtxprintf.h> - -#pragma pack(push, 1) - -#define NUM_IMAGE_LOCATION 32 - -//Entry Point Call -typedef void (*CIM_IMAGE_ENTRY) (void *pConfig); - -//Hook Call - -typedef struct _CIMFILEHEADER -{ - unsigned int AMDLogo; - unsigned long long CreatorID; - unsigned int Version1; - unsigned int Version2; - unsigned int Version3; - unsigned int ModuleInfoOffset; - unsigned int EntryPoint; - unsigned int ImageBase; - unsigned int RelocTableOffset; - unsigned int ImageSize; - unsigned short CheckSum; - unsigned char ImageType; - unsigned char Reserved2; -} CIMFILEHEADER; - -#ifndef BIT0 - #define BIT0 (1 << 0) -#endif -#ifndef BIT1 - #define BIT1 (1 << 1) -#endif -#ifndef BIT2 - #define BIT2 (1 << 2) -#endif -#ifndef BIT3 - #define BIT3 (1 << 3) -#endif -#ifndef BIT4 - #define BIT4 (1 << 4) -#endif -#ifndef BIT5 - #define BIT5 (1 << 5) -#endif -#ifndef BIT6 - #define BIT6 (1 << 6) -#endif -#ifndef BIT7 - #define BIT7 (1 << 7) -#endif -#ifndef BIT8 - #define BIT8 (1 << 8) -#endif -#ifndef BIT9 - #define BIT9 (1 << 9) -#endif -#ifndef BIT10 - #define BIT10 (1 << 10) -#endif -#ifndef BIT11 - #define BIT11 (1 << 11) -#endif -#ifndef BIT12 - #define BIT12 (1 << 12) -#endif -#ifndef BIT13 - #define BIT13 (1 << 13) -#endif -#ifndef BIT14 - #define BIT14 (1 << 14) -#endif -#ifndef BIT15 - #define BIT15 (1 << 15) -#endif -#ifndef BIT16 - #define BIT16 (1 << 16) -#endif -#ifndef BIT17 - #define BIT17 (1 << 17) -#endif -#ifndef BIT18 - #define BIT18 (1 << 18) -#endif -#ifndef BIT19 - #define BIT19 (1 << 19) -#endif -#ifndef BIT20 - #define BIT20 (1 << 20) -#endif -#ifndef BIT21 - #define BIT21 (1 << 21) -#endif -#ifndef BIT22 - #define BIT22 (1 << 22) -#endif -#ifndef BIT23 - #define BIT23 (1 << 23) -#endif -#ifndef BIT24 - #define BIT24 (1 << 24) -#endif -#ifndef BIT25 - #define BIT25 (1 << 25) -#endif -#ifndef BIT26 - #define BIT26 (1 << 26) -#endif -#ifndef BIT27 - #define BIT27 (1 << 27) -#endif -#ifndef BIT28 - #define BIT28 (1 << 28) -#endif -#ifndef BIT29 - #define BIT29 (1 << 29) -#endif -#ifndef BIT30 - #define BIT30 (1 << 30) -#endif -#ifndef BIT31 - #define BIT31 (1 << 31) -#endif - -#pragma pack(pop) - -typedef enum -{ - AccWidthUint8 = 0, - AccWidthUint16, - AccWidthUint32, -} ACC_WIDTH; - -#define S3_SAVE 0x80 - -#endif diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig deleted file mode 100644 index 7ab2cc1c07..0000000000 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ /dev/null @@ -1,210 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config SOUTHBRIDGE_AMD_CIMX_SB800 - bool - default n - select HAVE_USBDEBUG_OPTIONS - select AMD_SB_CIMX - select HAVE_CF9_RESET - select HAVE_CF9_RESET_PREPARE - select SOC_AMD_COMMON - select SOC_AMD_COMMON_BLOCK_ACPIMMIO - select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM - select SOC_AMD_COMMON_BLOCK_PCI_MMCONF - select BOOT_DEVICE_SUPPORTS_WRITES - -if SOUTHBRIDGE_AMD_CIMX_SB800 -config ENABLE_IDE_COMBINED_MODE - bool "Enable SATA IDE combined mode" - default n - help - If Combined Mode is enabled. IDE controller is exposed and - SATA controller has control over Port0 through Port3, - IDE controller has control over Port4 and Port5. - - If Combined Mode is disabled, IDE controller is hidden and - SATA controller has full control of all 6 Ports when operating in non-IDE mode. - -config IDE_COMBINED_MODE - hex - default 0x0 if ENABLE_IDE_COMBINED_MODE - default 0x1 if !ENABLE_IDE_COMBINED_MODE - -choice - prompt "SATA Mode" - default SB800_SATA_AHCI - help - Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. - The default is AHCI. - -config SB800_SATA_IDE - bool "NATIVE" - help - NATIVE does not require a ROM. - -config SB800_SATA_AHCI - bool "AHCI" - help - AHCI is the default and may work with or without AHCI ROM. It depends on the payload support. - For example, seabios does not require the AHCI ROM. - -config SB800_SATA_RAID - bool "RAID" - help - sb800 RAID mode must have the two required ROM files. - -endchoice - -config SB800_SATA_MODE - hex - depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) - default 0x0 if SB800_SATA_IDE - default 0x1 if SB800_SATA_RAID - default 0x2 if SB800_SATA_AHCI - -config SB_SUPERIO_HWM - bool - default n - -if SB800_SATA_AHCI -config AHCI_ROM_ID - string "AHCI device PCI IDs" - default "1002,4391" - -config SB800_AHCI_ROM - bool "Add a AHCI ROM" - -config AHCI_ROM_FILE - string "AHCI ROM path and filename" - depends on SB800_AHCI_ROM - default "site-local/sb800/ahci.bin" -endif - -if SB800_SATA_RAID -config RAID_ROM_ID - string "RAID device PCI IDs" - default "1002,4393" - help - 1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode - -config RAID_ROM_FILE - string "RAID ROM path and filename" - depends on SB800_SATA_RAID - default "site-local/sb800/raid.bin" - -config RAID_MISC_ROM_FILE - string "RAID Misc ROM path and filename" - default "site-local/sb800/misc.bin" - depends on SB800_SATA_RAID - -config RAID_MISC_ROM_POSITION - hex "RAID Misc ROM Position" - default 0xFFF00000 - depends on SB800_SATA_RAID - help - The RAID ROM requires that the MISC ROM is located between the range - 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. - The CONFIG_ROM_SIZE must larger than 0x100000. - -endif - -config SB800_IMC_FWM - bool "Add IMC firmware" - default n - select SPI_FLASH_HAS_VOLATILE_GROUP if SPI_FLASH - help - Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control. - -if SB800_IMC_FWM - -config SB800_IMC_FWM_FILE - string "IMC firmware path and filename" - default "3rdparty/blobs/southbridge/amd/sb800/imc.bin" - -choice - prompt "SB800 Firmware ROM Position" - -config SB800_FWM_AT_FFFA0000 - bool "0xFFFA0000" - help - The IMC and GEC ROMs requires a 'signature' located at one of several - fixed locations in memory. The location used shouldn't matter, just - select an area that doesn't conflict with anything else. - -config SB800_FWM_AT_FFF20000 - bool "0xFFF20000" - help - The IMC and GEC ROMs requires a 'signature' located at one of several - fixed locations in memory. The location used shouldn't matter, just - select an area that doesn't conflict with anything else. - -config SB800_FWM_AT_FFE20000 - depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 || BOARD_ROMSIZE_KB_2048 - bool "0xFFE20000" - help - The IMC and GEC ROMs requires a 'signature' located at one of several - fixed locations in memory. The location used shouldn't matter, just - select an area that doesn't conflict with anything else. - -config SB800_FWM_AT_FFC20000 - depends on BOARD_ROMSIZE_KB_8192 || BOARD_ROMSIZE_KB_4096 - bool "0xFFC20000" - help - The IMC and GEC ROMs requires a 'signature' located at one of several - fixed locations in memory. The location used shouldn't matter, just - select an area that doesn't conflict with anything else. - -config SB800_FWM_AT_FF820000 - depends on BOARD_ROMSIZE_KB_8192 - bool "0xFF820000" - help - The IMC and GEC ROMs requires a 'signature' located at one of several - fixed locations in memory. The location used shouldn't matter, just - select an area that doesn't conflict with anything else. - -endchoice - -config SB800_FWM_POSITION - hex - default 0xFFFA0000 if SB800_FWM_AT_FFFA0000 - default 0xFFF20000 if SB800_FWM_AT_FFF20000 - default 0xFFE20000 if SB800_FWM_AT_FFE20000 - default 0xFFC20000 if SB800_FWM_AT_FFC20000 - default 0xFF820000 if SB800_FWM_AT_FF820000 - -endif #SB800_IMC_FWM - -config EHCI_BAR - hex - default 0xfef00000 - -choice - prompt "Fan Control" - default SB800_NO_FAN_CONTROL - help - Select the method of SB800 fan control to be used. None would be - for either fixed maximum speed fans connected to the SB800 or for - an external chip controlling the fan speeds. Manual control sets - up the SB800 fan control registers. IMC fan control uses the SB800 - IMC to actively control the fan speeds. - -config SB800_NO_FAN_CONTROL - bool "None" - help - No SB800 Fan control - Do not set up the SB800 fan control registers. - -config SB800_MANUAL_FAN_CONTROL - bool "Manual" - help - Configure the SB800 fan control registers in devicetree.cb. - -config SB800_IMC_FAN_CONTROL - bool "IMC Based" - depends on SB800_IMC_FWM - help - Set up the SB800 to use the IMC based Fan controller. This requires - the IMC ROM from AMD. Configure the registers in devicetree.cb. - -endchoice - -endif #SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc deleted file mode 100644 index 1ac69aede2..0000000000 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ /dev/null @@ -1,88 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -# SB800 Platform Files - -bootblock-y += bootblock.c - -romstage-y += cfg.c -romstage-y += early.c -romstage-y += smbus.c smbus_spd.c - -ramstage-y += cfg.c -ramstage-y += late.c - -all-y += reset.c - -ramstage-$(CONFIG_SB800_MANUAL_FAN_CONTROL) += fan.c -ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c - -postcar-y += ramtop.c -romstage-y += ramtop.c -ramstage-y += ramtop.c - -bootblock-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c -romstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c - -ramstage-y += smbus.c -ramstage-y += lpc.c - -ifeq ($(CONFIG_SB800_SATA_AHCI), y) -ifdef CONFIG_SB800_AHCI_ROM - stripped_ahci_rom_id = $(call strip_quotes,$(CONFIG_AHCI_ROM_ID)) - cbfs-files-y += pci$(stripped_ahci_rom_id).rom - pci$(stripped_ahci_rom_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_ROM_FILE)) - pci$(stripped_ahci_rom_id).rom-type := optionrom -endif -endif - -ifeq ($(CONFIG_SB800_SATA_RAID), y) - stripped_raid_rom_id = $(call strip_quotes,$(CONFIG_RAID_ROM_ID)) - cbfs-files-y += pci$(stripped_raid_rom_id).rom - pci$(stripped_raid_rom_id).rom-file := $(call strip_quotes,$(CONFIG_RAID_ROM_FILE)) - pci$(stripped_raid_rom_id).rom-type := optionrom - - cbfs-files-y += raid/misc.bin - raid/misc.bin-file := $(call strip_quotes,$(CONFIG_RAID_MISC_ROM_FILE)) - raid/misc.bin-position := $(CONFIG_RAID_MISC_ROM_POSITION) - raid/misc.bin-type := raw -endif - -ifeq ($(CONFIG_SB800_IMC_FWM), y) - -# ROMSIG At ROMBASE + 0x20000: -# +-----------+---------------+----------------+------------+ -# |0x55AA55AA |EC ROM Address |GEC ROM Address | | -# +-----------+---------------+----------------+------------+ -# EC ROM should be 64K aligned. -SB800_FWM_POSITION=$(shell printf %u $(CONFIG_SB800_FWM_POSITION)) -#assume the cbfs header is less than 128 bytes. -ROMSIG_SIZE=16 - -SB800_IMC_POSITION=$(call int-align,$(call add-int,$(SB800_FWM_POSITION) $(ROMSIG_SIZE) 128),65536) - -$(obj)/coreboot_SB800_romsig.bin: \ - $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) \ - $(obj)/config.h \ - $(obj)/mainboard/$(MAINBOARDDIR)/static.c - echo " SB800 FW $@" - for fwm in 1437226410 \ - $(SB800_IMC_POSITION) \ - 0 \ - 0 ; do \ - echo $$fwm | LC_ALL=C awk '{printf ("%c%c%c%c", $$1 % 256, int($$1/256) % 256, int($$1/65536) % 256, int($$1/16777216));}'; \ - done > $@ - -cbfs-files-y += SB800/fwm -SB800/fwm-file := $(obj)/coreboot_SB800_romsig.bin -SB800/fwm-position := $(SB800_FWM_POSITION) -SB800/fwm-type := raw - -cbfs-files-y += SB800/imc -SB800/imc-file := $(call strip_quotes, $(CONFIG_SB800_IMC_FWM_FILE)) -SB800/imc-position := $(SB800_IMC_POSITION) -SB800/imc-type := raw - -endif diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h deleted file mode 100644 index 760088632e..0000000000 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ - -#include <stddef.h> - -typedef unsigned long long PLACEHOLDER; - -#ifndef SBOEM_ACPI_RESTORE_SWSMI - #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 - #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 -#endif - -#ifndef _AMD_NB_CIM_X_PROTOCOL_H_ - -/* -/// Extended PCI Address -typedef struct _EXT_PCI_ADDR { - UINT32 Reg :16; ///< / PCI Register - UINT32 Func:3; ///< / PCI Function - UINT32 Dev :5; ///< / PCI Device - UINT32 Bus :8; ///< / PCI Address -} EXT_PCI_ADDR; - -/// PCI Address -typedef union _PCI_ADDR { - UINT32 ADDR; ///< / 32 bit Address - EXT_PCI_ADDR Addr; ///< / Extended PCI Address -} PCI_ADDR; -*/ -#endif -#define FIXUP_PTR(ptr) ptr - -#if CONFIG(SB800_IMC_FWM) - #define IMC_ENABLE_OVER_WRITE 0x01 -#endif - -#include "AmdSbLib.h" -#include "Amd.h" -#include <SB800.h> -#include <SBTYPE.h> -#include <ACPILIB.h> -#include <SBDEF.h> -#include <AMDSBLIB.h> -#include <SBSUBFUN.h> -#include "platform_cfg.h" -#include <OEM.h> -#include <AMD.h> - -//------------------------------------------------------------------------------------------------------------------------// -/** - * SB_CIMx_PARAMETER 0 1 2 Default Value When CIMx Take over - * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable - * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal - * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable - * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00) - * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable - * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL) - * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable - * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable - * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable - * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable - * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable - * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable - * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable - * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable - * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Never Power down (0x11) - * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00) - * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz - * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable - * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00) - * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable - * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable - * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable - * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable - * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable - * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable - * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable - * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable - * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable - */ -#define SB_CIMx_PARAMETER 0x02 - -// Generic -#define cimSpreadSpectrumDefault TRUE -#define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x01 // Enable -#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz -#define cimSioHwmPortEnableDefault FALSE -// GPP/AB Controller -#define cimNbSbGen2Default TRUE -#define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE -// USB Controller -#define cimUsbPhyPowerDownDefault FALSE -// GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 -// Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE -// Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE - -#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" -#include <spi-generic.h> - -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 - -#endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb800/acpi/audio.asl b/src/southbridge/amd/cimx/sb800/acpi/audio.asl deleted file mode 100644 index 0d5f00d33c..0000000000 --- a/src/southbridge/amd/cimx/sb800/acpi/audio.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device(AZHD) { /* 0:14.2 - HD Audio */ - Name(_ADR, 0x00140002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } -} /* end AZHD */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl deleted file mode 100644 index 5527660255..0000000000 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ /dev/null @@ -1,166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* System Bus */ -/* _SB.PCI0 */ - -/* Operating System Capabilities Method */ -Method(_OSC,4) -{ - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) - { - /* Let OS control everything */ - Return (Arg3) - } Else { - CreateDWordField(Arg3,0,CDW1) - CDW1 |= 4 // Unrecognized UUID - Return (Arg3) - } -} - -Method(_BBN, 0) { /* Bus number = 0 */ - Return (0) -} -Method(_STA, 0) { - /* DBGO("\\_SB\\PCI0\\_STA\n") */ - Return (0x0b) /* Status is visible */ -} - -Method(_PRT,0) { - If(PICM){ Return(APR0) } /* APIC mode */ - Return (PR0) /* PIC Mode */ -} /* end _PRT */ - -/* Describe the Southbridge devices */ - -#include "pcie.asl" - -Device(STCR) { - Name(_ADR, 0x00110000) - #include "acpi/sata.asl" -} /* end STCR */ - -#include "usb.asl" - -Device(SBUS) { - Name(_ADR, 0x00140000) -} /* end SBUS */ - -#include "audio.asl" - -#include "lpc.asl" - -/* PCI bridge */ -Device(PIBR) { - Name(_ADR, 0x00140004) - Name(_PRW, Package() {0x18, 4}) - - Method(_PRT, 0) { - Return (PCIB) - } -} /* end HostPciBr */ - -Device(ACAD) { - Name(_ADR, 0x00140005) -} /* end Ac97audio */ - -Device(ACMD) { - Name(_ADR, 0x00140006) -} /* end Ac97modem */ - -Name(CRES, ResourceTemplate() { - /* Set the Bus number and Secondary Bus number for the PCI0 device - * The Secondary bus range for PCI0 lets the system - * know what bus values are allowed on the downstream - * side of this PCI bus if there is a PCI-PCI bridge. - * PCI buses can have 256 secondary buses which - * range from [0-0xFF] but they do not need to be - * sequential. - */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x00FF, /* range maximum */ - 0x0000, /* translation */ - 0x0100, /* length */ - ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ - - IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ - ) - - WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0D00, /* range minimum */ - 0xFFFF, /* range maximum */ - 0x0000, /* translation */ - 0xF300 /* length */ - ) - - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ - - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) -}) /* End Name(_SB.PCI0.CRES) */ - -Method(_CRS, 0) { - /* DBGO("\\_SB\\PCI0\\_CRS\n") */ - CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - MM1B = TOM1 - Local0 = 0x10000000 << 4 - Local0 -= TOM1 - MM1L = Local0 - - Return (CRES) /* note to change the Name buffer */ -} /* end of Method(_SB.PCI0._CRS) */ - -/* - * - * FIRST METHOD CALLED UPON BOOT - * - * 1. If debugging, print current OS and ACPI interpreter. - * 2. Get PCI Interrupt routing from ACPI VSM, this - * value is based on user choice in BIOS setup. - */ -Method(_INI, 0) { - /* DBGO("\\_SB\\_INI\n") */ - /* DBGO(" DSDT.ASL code from ") */ - /* DBGO(__DATE__) */ - /* DBGO(" ") */ - /* DBGO(__TIME__) */ - /* DBGO("\n Sleep states supported: ") */ - /* DBGO("\n") */ - /* DBGO(" \\_OS=") */ - /* DBGO(\_OS) */ - /* DBGO("\n \\_REV=") */ - /* DBGO(\_REV) */ - /* DBGO("\n") */ - - /* On older chips, clear PciExpWakeDisEn */ - /*if (\SBRI <= 0x13) { - * \PWDE = 0 - * } - */ -} /* End Method(_SB._INI) */ - -Scope(\){ - - #include "misc_io.asl" - -} diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl deleted file mode 100644 index 151b015074..0000000000 --- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* 0:14.3 - LPC */ -Device(LIBR) { - Name(_ADR, 0x00140003) - - /* Real Time Clock Device */ - Device(RTC0) { - Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){8} - IO(Decode16,0x0070, 0x0070, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ - - Device(TMR) { /* Timer */ - Name(_HID,EISAID("PNP0100")) /* System Timer */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){0} - IO(Decode16, 0x0040, 0x0040, 0, 4) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ - - Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x0061, 0x0061, 0, 1) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ - - Device(PIC) { - Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ - Name(_CRS, ResourceTemplate() { - IRQNoFlags(){2} - IO(Decode16,0x0020, 0x0020, 0, 2) - IO(Decode16,0x00A0, 0x00A0, 0, 2) - }) - } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ - - Device(MAD) { /* 8257 DMA */ - Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ - Name(_CRS, ResourceTemplate() { - DMA(Compatibility,BusMaster,Transfer8){4} - IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) - IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) - IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) - IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) - IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) - IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) - }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ - } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ - - Device(COPR) { - Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ - Name(_CRS, ResourceTemplate() { - IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) - IRQNoFlags(){13} - }) - } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ - #include "acpi/superio.asl" -} /* end LIBR */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl b/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl deleted file mode 100644 index b8296fb066..0000000000 --- a/src/southbridge/amd/cimx/sb800/acpi/misc_io.asl +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - - -/* Client Management index/data registers */ -OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) - Field(CMT, ByteAcc, NoLock, Preserve) { - CMTI, 8, - /* Client Management Data register */ - G64E, 1, - G64O, 1, - G32O, 2, - , 2, - GPSL, 2, -} - -/* GPM Port register */ -OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) - Field(GPT, ByteAcc, NoLock, Preserve) { - GPB0,1, - GPB1,1, - GPB2,1, - GPB3,1, - GPB4,1, - GPB5,1, - GPB6,1, - GPB7,1, -} - -/* Flash ROM program enable register */ -OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) - Field(FRE, ByteAcc, NoLock, Preserve) { - , 0x00000006, - FLRE, 0x00000001, -} - -/* PM2 index/data registers */ -OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) - Field(PM2R, ByteAcc, NoLock, Preserve) { - PM2I, 0x00000008, - PM2D, 0x00000008, -} - -/* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ -OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) - Field(PIOR, ByteAcc, NoLock, Preserve) { - PIOI, 0x00000008, - PIOD, 0x00000008, -} -IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { - , 1, /* MiscControl */ - T1EE, 1, - T2EE, 1, - Offset(0x01), /* MiscStatus */ - , 1, - T1E, 1, - T2E, 1, - Offset(0x04), /* SmiWakeUpEventEnable3 */ - , 7, - SSEN, 1, - Offset(0x07), /* SmiWakeUpEventStatus3 */ - , 7, - CSSM, 1, - Offset(0x10), /* AcpiEnable */ - , 6, - PWDE, 1, - Offset(0x1C), /* ProgramIoEnable */ - , 3, - MKME, 1, - IO3E, 1, - IO2E, 1, - IO1E, 1, - IO0E, 1, - Offset(0x1D), /* IOMonitorStatus */ - , 3, - MKMS, 1, - IO3S, 1, - IO2S, 1, - IO1S, 1, - IO0S,1, - Offset(0x20), /* AcpiPmEvtBlk. TODO: should be 0x60 */ - APEB, 16, - Offset(0x36), /* GEvtLevelConfig */ - , 6, - ELC6, 1, - ELC7, 1, - Offset(0x37), /* GPMLevelConfig0 */ - , 3, - PLC0, 1, - PLC1, 1, - PLC2, 1, - PLC3, 1, - PLC8, 1, - Offset(0x38), /* GPMLevelConfig1 */ - , 1, - PLC4, 1, - PLC5, 1, - , 1, - PLC6, 1, - PLC7, 1, - Offset(0x3B), /* PMEStatus1 */ - GP0S, 1, - GM4S, 1, - GM5S, 1, - APS, 1, - GM6S, 1, - GM7S, 1, - GP2S, 1, - STSS, 1, - Offset(0x55), /* SoftPciRst */ - SPRE, 1, - , 1, - , 1, - PNAT, 1, - PWMK, 1, - PWNS, 1, - - Offset(0x65), /* UsbPMControl */ - , 4, - URRE, 1, - Offset(0x68), /* MiscEnable68 */ - , 3, - TMTE, 1, - , 1, - Offset(0x92), /* GEVENTIN */ - , 7, - E7IS, 1, - Offset(0x96), /* GPM98IN */ - G8IS, 1, - G9IS, 1, - Offset(0x9A), /* EnhanceControl */ - ,7, - HPDE, 1, - Offset(0xA8), /* PIO7654Enable */ - IO4E, 1, - IO5E, 1, - IO6E, 1, - IO7E, 1, - Offset(0xA9), /* PIO7654Status */ - IO4S, 1, - IO5S, 1, - IO6S, 1, - IO7S, 1, -} - -/* PM1 Event Block -* First word is PM1_Status, Second word is PM1_Enable -*/ -OperationRegion(P1EB, SystemIO, APEB, 0x04) - Field(P1EB, ByteAcc, NoLock, Preserve) { - TMST, 1, - , 3, - BMST, 1, - GBST, 1, - Offset(0x01), - PBST, 1, - , 1, - RTST, 1, - , 3, - PWST, 1, - SPWS, 1, - Offset(0x02), - TMEN, 1, - , 4, - GBEN, 1, - Offset(0x03), - PBEN, 1, - , 1, - RTEN, 1, - , 3, - PWDA, 1, -} diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl deleted file mode 100644 index f69ba1db24..0000000000 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ /dev/null @@ -1,481 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope(\) { - /* PCI IRQ mapping registers, C00h-C01h. */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) - Field(PRQM, ByteAcc, NoLock, Preserve) { - PRQI, 0x00000008, - PRQD, 0x00000008, /* Offset: 1h */ - } - IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { - PIRA, 0x00000008, /* Index 0 */ - PIRB, 0x00000008, /* Index 1 */ - PIRC, 0x00000008, /* Index 2 */ - PIRD, 0x00000008, /* Index 3 */ - PIRE, 0x00000008, /* Index 4 */ - PIRF, 0x00000008, /* Index 5 */ - PIRG, 0x00000008, /* Index 6 */ - PIRH, 0x00000008, /* Index 7 */ - } - - /* PCI Error control register */ - OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) - Field(PERC, ByteAcc, NoLock, Preserve) { - SENS, 0x00000001, - PENS, 0x00000001, - SENE, 0x00000001, - PENE, 0x00000001, - } -} - -Scope(\_SB) { - Field(PCFG, ByteAcc, NoLock, Preserve) { - /* Byte offsets are computed using the following technique: - * ((bus number + 1) * ((device number * 8) * 4096)) + register offset - * The 8 comes from 8 functions per device, and 4096 bytes per function config space - */ - Offset(0x00088024), /* SATA reg 24h Bus 0, Device 17, Function 0 */ - STB5, 32, - Offset(0x00098042), /* OHCI0 reg 42h - Bus 0, Device 19, Function 0 */ - PT0D, 1, - PT1D, 1, - PT2D, 1, - PT3D, 1, - PT4D, 1, - PT5D, 1, - PT6D, 1, - PT7D, 1, - PT8D, 1, - PT9D, 1, - Offset(0x000A0004), /* SMBUS reg 4h - Bus 0, Device 20, Function 0 */ - SBIE, 1, - SBME, 1, - Offset(0x000A0008), /* SMBUS reg 8h - Bus 0, Device 20, Function 0 */ - SBRI, 8, - Offset(0x000A0014), /* SMBUS reg 14h - Bus 0, Device 20, Function 0 */ - SBB1, 32, - Offset(0x000A0078), /* SMBUS reg 78h - Bus 0, Device 20, Function 0 */ - ,14, - P92E, 1, /* Port92 decode enable */ - } - - OperationRegion(SB5, SystemMemory, STB5, 0x1000) - Field(SB5, AnyAcc, NoLock, Preserve){ - /* Port 0 */ - Offset(0x120), /* Port 0 Task file status */ - P0ER, 1, - , 2, - P0DQ, 1, - , 3, - P0BY, 1, - Offset(0x128), /* Port 0 Serial ATA status */ - P0DD, 4, - , 4, - P0IS, 4, - Offset(0x12C), /* Port 0 Serial ATA control */ - P0DI, 4, - Offset(0x130), /* Port 0 Serial ATA error */ - , 16, - P0PR, 1, - - /* Port 1 */ - offset(0x1A0), /* Port 1 Task file status */ - P1ER, 1, - , 2, - P1DQ, 1, - , 3, - P1BY, 1, - Offset(0x1A8), /* Port 1 Serial ATA status */ - P1DD, 4, - , 4, - P1IS, 4, - Offset(0x1AC), /* Port 1 Serial ATA control */ - P1DI, 4, - Offset(0x1B0), /* Port 1 Serial ATA error */ - , 16, - P1PR, 1, - - /* Port 2 */ - Offset(0x220), /* Port 2 Task file status */ - P2ER, 1, - , 2, - P2DQ, 1, - , 3, - P2BY, 1, - Offset(0x228), /* Port 2 Serial ATA status */ - P2DD, 4, - , 4, - P2IS, 4, - Offset(0x22C), /* Port 2 Serial ATA control */ - P2DI, 4, - Offset(0x230), /* Port 2 Serial ATA error */ - , 16, - P2PR, 1, - - /* Port 3 */ - Offset(0x2A0), /* Port 3 Task file status */ - P3ER, 1, - , 2, - P3DQ, 1, - , 3, - P3BY, 1, - Offset(0x2A8), /* Port 3 Serial ATA status */ - P3DD, 4, - , 4, - P3IS, 4, - Offset(0x2AC), /* Port 3 Serial ATA control */ - P3DI, 4, - Offset(0x2B0), /* Port 3 Serial ATA error */ - , 16, - P3PR, 1, - } - - Name(IRQB, ResourceTemplate(){ - IRQ(Level,ActiveLow,Shared){15} - }) - - Name(IRQP, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} - }) - - Name(PITF, ResourceTemplate(){ - IRQ(Level,ActiveLow,Exclusive){9} - }) - - Device(INTA) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 1) - - Method(_STA, 0) { - if (PIRA) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTA._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKA\\_DIS\n") */ - PIRA = 0 - } /* End Method(_SB.INTA._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKA\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTA._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKA\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRA - Return (IRQB) - } /* Method(_SB.INTA._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKA\\_SRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRA = Local0 - } /* End Method(_SB.INTA._SRS) */ - } /* End Device(INTA) */ - - Device(INTB) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 2) - - Method(_STA, 0) { - if (PIRB) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTB._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKB\\_DIS\n") */ - PIRB = 0 - } /* End Method(_SB.INTB._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKB\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTB._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRB - Return (IRQB) - } /* Method(_SB.INTB._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKB\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRB = Local0 - } /* End Method(_SB.INTB._SRS) */ - } /* End Device(INTB) */ - - Device(INTC) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 3) - - Method(_STA, 0) { - if (PIRC) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTC._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKC\\_DIS\n") */ - PIRC = 0 - } /* End Method(_SB.INTC._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKC\\_PRS\n") */ - Return(IRQP) - } /* Method(_SB.INTC._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRC - Return (IRQB) - } /* Method(_SB.INTC._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKC\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRC = Local0 - } /* End Method(_SB.INTC._SRS) */ - } /* End Device(INTC) */ - - Device(INTD) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 4) - - Method(_STA, 0) { - if (PIRD) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTD._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKD\\_DIS\n") */ - PIRD = 0 - } /* End Method(_SB.INTD._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKD\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTD._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRD - Return (IRQB) - } /* Method(_SB.INTD._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKD\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRD = Local0 - } /* End Method(_SB.INTD._SRS) */ - } /* End Device(INTD) */ - - Device(INTE) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 5) - - Method(_STA, 0) { - if (PIRE) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTE._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKE\\_DIS\n") */ - PIRE = 0 - } /* End Method(_SB.INTE._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKE\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTE._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRE - Return (IRQB) - } /* Method(_SB.INTE._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKE\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRE = Local0 - } /* End Method(_SB.INTE._SRS) */ - } /* End Device(INTE) */ - - Device(INTF) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 6) - - Method(_STA, 0) { - if (PIRF) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTF._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKF\\_DIS\n") */ - PIRF = 0 - } /* End Method(_SB.INTF._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKF\\_PRS\n") */ - Return (PITF) - } /* Method(_SB.INTF._PRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRF - Return (IRQB) - } /* Method(_SB.INTF._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKF\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRF = Local0 - } /* End Method(_SB.INTF._SRS) */ - } /* End Device(INTF) */ - - Device(INTG) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 7) - - Method(_STA, 0) { - if (PIRG) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTG._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKG\\_DIS\n") */ - PIRG = 0 - } /* End Method(_SB.INTG._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKG\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTG._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRG - Return (IRQB) - } /* Method(_SB.INTG._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKG\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRG = Local0 - } /* End Method(_SB.INTG._SRS) */ - } /* End Device(INTG) */ - - Device(INTH) { - Name(_HID, EISAID("PNP0C0F")) - Name(_UID, 8) - - Method(_STA, 0) { - if (PIRH) { - Return (0x0b) /* sata is invisible */ - } else { - Return (0x09) /* sata is disabled */ - } - } /* End Method(_SB.INTH._STA) */ - - Method(_DIS ,0) { - /* DBGO("\\_SB\\LNKH\\_DIS\n") */ - PIRH = 0 - } /* End Method(_SB.INTH._DIS) */ - - Method(_PRS ,0) { - /* DBGO("\\_SB\\LNKH\\_PRS\n") */ - Return (IRQP) - } /* Method(_SB.INTH._CRS) */ - - Method(_CRS ,0) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(IRQB, 0x1, IRQN) - IRQN = 1 << PIRH - Return (IRQB) - } /* Method(_SB.INTH._CRS) */ - - Method(_SRS, 1) { - /* DBGO("\\_SB\\LNKH\\_CRS\n") */ - CreateWordField(ARG0, 1, IRQM) - - /* Use lowest available IRQ */ - FindSetRightBit(IRQM, Local0) - if (Local0) { - Local0-- - } - PIRH = Local0 - } /* End Method(_SB.INTH._SRS) */ - } /* End Device(INTH) */ - - } /* End Scope(_SB) */ diff --git a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl b/src/southbridge/amd/cimx/sb800/acpi/smbus.asl deleted file mode 100644 index b81c5b1c37..0000000000 --- a/src/southbridge/amd/cimx/sb800/acpi/smbus.asl +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* SMBUS Support */ -Mutex (SBX0, 0x00) -OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) - Field (SMB0, ByteAcc, NoLock, Preserve) { - HSTS, 8, /* SMBUS status */ - SSTS, 8, /* SMBUS slave status */ - HCNT, 8, /* SMBUS control */ - HCMD, 8, /* SMBUS host cmd */ - HADD, 8, /* SMBUS address */ - DAT0, 8, /* SMBUS data0 */ - DAT1, 8, /* SMBUS data1 */ - BLKD, 8, /* SMBUS block data */ - SCNT, 8, /* SMBUS slave control */ - SCMD, 8, /* SMBUS shadow cmd */ - SEVT, 8, /* SMBUS slave event */ - SDAT, 8 /* SMBUS slave data */ -} - -Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ - HSTS = 0x1e - Local0 = 0xfa - While ((HSTS & 0x1e) != 0) && (Local0 > 0)) { - Stall (0x64) - Local0-- - } - - Return (Local0) -} - -Method (SWTC, 1, NotSerialized) { - Local0 = Arg0 - Local2 = 0x07 - Local1 = 1 - While (Local1 == 1) { - Local3 = HSTS & 0x1e - If (Local3 != 0) { /* read success */ - If (Local3 != 0x02) { - Local2 = 0 - } - - Local1 = 0 - } - Else { - If (Local0 < 0x0A) { /* read failure */ - Local2 = 0x10 - Local1 = 0 - } - Else { - Sleep (0x0A) /* 10 ms, try again */ - Local0 -= 0x0a - } - } - } - - Return (Local2) -} - -Method (SMBR, 3, NotSerialized) { - Local0 = 0x07 - If (Acquire (SBX0, 0xFFFF) == 0) { - Local0 = WCLR () /* clear SMBUS status register before read data */ - If (Local0 == 0) { - Release (SBX0) - Return (0x0) - } - - HSTS = 0x1f - HADD = (Arg1 << 1) | 1 - HCMD = Arg2 - If (Arg0 == 0x07) { - HCNT = 0x48 /* read byte */ - } - - Local1 = SWTC (0x03E8) /* 1000 ms */ - If (Local1 == 0) { - If (Arg0 == 0x07) { - Local0 = DAT0 - } - } - Else { - Local0 = Local1 - } - - Release (SBX0) - } - - /* DBGO("the value of SMBusData0 register ") */ - /* DBGO(Arg2) */ - /* DBGO(" is ") */ - /* DBGO(Local0) */ - /* DBGO("\n") */ - - Return (Local0) -} diff --git a/src/southbridge/amd/cimx/sb800/acpi/usb.asl b/src/southbridge/amd/cimx/sb800/acpi/usb.asl deleted file mode 100644 index 35c8c7e459..0000000000 --- a/src/southbridge/amd/cimx/sb800/acpi/usb.asl +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* 0:12.0 - OHCI */ -Device(UOH1) { - Name(_ADR, 0x00120000) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH1 */ - -/* 0:12.2 - EHCI */ -Device(UOH2) { - Name(_ADR, 0x00120002) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH2 */ - -/* 0:13.0 - OHCI */ -Device(UOH3) { - Name(_ADR, 0x00130000) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH3 */ - -/* 0:13.2 - EHCI */ -Device(UOH4) { - Name(_ADR, 0x00130002) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH4 */ - -/* 0:16.0 - OHCI */ -Device(UOH5) { - Name(_ADR, 0x00160000) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH5 */ - -/* 0:16.2 - EHCI */ -Device(UOH6) { - Name(_ADR, 0x00160002) - Name(_PRW, Package() {0x0B, 3}) -} /* end UOH5 */ - -Device(UEH1) { - Name(_ADR, 0x00140005) - Name(_PRW, Package() {0x0B, 3}) -} /* end UEH1 */ diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h deleted file mode 100644 index b3fb37dbc8..0000000000 --- a/src/southbridge/amd/cimx/sb800/amd_pci_int_defs.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_PCI_INT_DEFS_H -#define AMD_PCI_INT_DEFS_H - -/* - * PIRQ and device routing - these define the index - * into the FCH PCI_INTR 0xC00/0xC01 interrupt - * routing table - */ -#define FCH_INT_TABLE_SIZE 0x54 - -#define PIRQ_NC 0x1F /* Not Used */ -#define PIRQ_A 0x00 /* INT A */ -#define PIRQ_B 0x01 /* INT B */ -#define PIRQ_C 0x02 /* INT C */ -#define PIRQ_D 0x03 /* INT D */ -#define PIRQ_E 0x04 /* INT E */ -#define PIRQ_F 0x05 /* INT F */ -#define PIRQ_G 0x06 /* INT G */ -#define PIRQ_H 0x07 /* INT H */ -#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ -#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ -#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ -#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ -#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ -#define PIRQ_SIRQB 0x0D /* Serial IRQ INTB */ -#define PIRQ_SIRQC 0x0E /* Serial IRQ INTC */ -#define PIRQ_SIRQD 0x0F /* Serial IRQ INTD */ -#define PIRQ_SCI 0x10 /* SCI IRQ */ -#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ -#define PIRQ_ASF 0x12 /* ASF */ -#define PIRQ_HDA 0x13 /* HDA 14h.2 */ -#define PIRQ_FC 0x14 /* FC */ -#define PIRQ_GEC 0x15 /* GEC */ -#define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_IMC0 0x20 /* IMC INT0 */ -#define PIRQ_IMC1 0x21 /* IMC INT1 */ -#define PIRQ_IMC2 0x22 /* IMC INT2 */ -#define PIRQ_IMC3 0x23 /* IMC INT3 */ -#define PIRQ_IMC4 0x24 /* IMC INT4 */ -#define PIRQ_IMC5 0x25 /* IMC INT5 */ -#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ -#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ -#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ -#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ -#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ -#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ -#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ -#define PIRQ_IDE 0x40 /* IDE 14h.1 */ -#define PIRQ_SATA 0x41 /* SATA 11h.0 */ -#define PIRQ_GPP0 0x50 /* GPP INT 0 */ -#define PIRQ_GPP1 0x51 /* GPP INT 1 */ -#define PIRQ_GPP2 0x52 /* GPP INT 2 */ -#define PIRQ_GPP3 0x53 /* GPP INT 3 */ - -#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h deleted file mode 100644 index 578c2b7f57..0000000000 --- a/src/southbridge/amd/cimx/sb800/amd_pci_int_types.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_PCI_INT_TYPES_H -#define AMD_PCI_INT_TYPES_H - -const char *intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" -}; - -#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c deleted file mode 100644 index 636e5a8eec..0000000000 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <arch/bootblock.h> -#include <device/pci_ops.h> - -static void enable_rom(void) -{ - u16 word; - u32 dword; - const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); - /* SB800 LPC Bridge 0:20:3:44h. - * BIT6: Port Enable for serial port 0x3f8-0x3ff - * BIT29: Port Enable for KBC port 0x60 and 0x64 - * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62 - */ - dword = pci_s_read_config32(dev, 0x44); - //dword |= (1<<6) | (1<<29) | (1<<30); - /* Turn on all of LPC IO Port decode enable */ - dword = 0xffffffff; - pci_s_write_config32(dev, 0x44, dword); - - /* SB800 LPC Bridge 0:20:3:48h. - * BIT0: Port Enable for SuperIO 0x2E-0x2F - * BIT1: Port Enable for SuperIO 0x4E-0x4F - * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C) - * BIT6: Port Enable for RTC IO 0x70-0x73 - * BIT21: Port Enable for Port 0x80 - */ - dword = pci_s_read_config32(dev, 0x48); - dword |= (1 << 0) | (1 << 1) | (1 << 4) | (1 << 6) | (1 << 21); - pci_s_write_config32(dev, 0x48, dword); - - /* Enable ROM access */ - word = pci_s_read_config16(dev, 0x6c); - word = 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6); - pci_s_write_config16(dev, 0x6c, word); -} - -static void enable_prefetch(void) -{ - u32 dword; - const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); - - /* Enable PrefetchEnSPIFromHost */ - dword = pci_s_read_config32(dev, 0xb8); - pci_s_write_config32(dev, 0xb8, dword | (1 << 24)); -} - -static void enable_spi_fast_mode(void) -{ - u32 dword; - const pci_devfn_t dev = PCI_DEV(0, 0x14, 0x03); - - // set temp MMIO base - volatile u32 *spi_base = (void *)0xa0000000; - u32 save = pci_s_read_config32(dev, 0xa0); - pci_s_write_config32(dev, 0xa0, (u32)spi_base | 2); - - // early enable of SPI 33 MHz fast mode read - dword = spi_base[3]; - spi_base[3] = (dword & ~(3 << 14)) | (1 << 14); - spi_base[0] = spi_base[0] | (1 << 18); // fast read enable - - pci_s_write_config32(dev, 0xa0, save); -} - -static void enable_clocks(void) -{ - u32 reg32; - - // Program SB800 MiscClkCntrl register to configure clock output on the - // 14M_25M_48M_OSC ball usually used for the Super-I/O. - // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz, - // which is the SB800's power up default. We could switch back to 14 - // in the mainboard's romstage.c, but then the clock frequency would - // change twice. - reg32 = misc_read32(0x40); - reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) -#if !CONFIG(SUPERIO_WANTS_14MHZ_CLOCK) - reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz -#endif - misc_write32(0x40, reg32); -} - -void bootblock_early_southbridge_init(void) -{ - /* Setup the ROM access for 2M */ - enable_rom(); - enable_prefetch(); - enable_spi_fast_mode(); - - // Program AcpiMmioEn to enable MMIO access to MiscCntrl register - enable_acpimmio_decode_pm24(); - enable_clocks(); -} diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c deleted file mode 100644 index f1ac4c920c..0000000000 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/hpet.h> /* Include this before OEM.h to have HPET_BASE_ADDRESS from arch/x86 */ -#include "SBPLATFORM.h" -#include "cfg.h" -#include <OEM.h> - -#include <acpi/acpi.h> - -/** - * @brief South Bridge CIMx configuration - * - * should be called before executing CIMx functions. - * this function will be called in romstage and ramstage. - */ -void sb800_cimx_config(AMDSBCFG *sb_config) -{ - uint16_t bios_size = BIOS_SIZE; - if (!sb_config) - return; - - sb_config->S3Resume = acpi_is_wakeup_s3(); - - /* header */ - sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; - - /* static Build Parameters */ - sb_config->BuildParameters.BiosSize = bios_size; - sb_config->BuildParameters.LegacyFree = LEGACY_FREE; - sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; - sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; - sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; - sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; - sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; - sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; - sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; - sb_config->BuildParameters.SioHwmBaseAddress = SIO_HWM_BASE_ADDRESS; - sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; - sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS; - sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; - sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; - sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; - sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; - sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; - sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; - sb_config->BuildParameters.OhciSsid = OHCI_SSID; - sb_config->BuildParameters.EhciSsid = EHCI_SSID; - sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; - sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; - sb_config->BuildParameters.IdeSsid = IDE_SSID; - sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; - sb_config->BuildParameters.LpcSsid = LPC_SSID; - sb_config->BuildParameters.PCIBSsid = PCIB_SSID; - sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type; - sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; - sb_config->BuildParameters.ImcEnableOverWrite = IMC_ENABLE_OVER_WRITE; - - /* General */ - sb_config->SpreadSpectrum = SPREAD_SPECTRUM; - sb_config->PciClks = PCI_CLOCK_CTRL; - sb_config->HpetTimer = HPET_TIMER; - sb_config->SbSpiSpeedSupport = 1; - - /* USB */ - sb_config->USBMODE.UsbModeReg = USB_CONFIG; - sb_config->SbUsbPll = 0; - /* CG PLL multiplier for USB Rx 1.1 mode (0=disable, 1=enable) */ - sb_config->UsbRxMode = USB_RX_MODE; - - /* SATA */ - sb_config->SataClass = SATA_MODE; - sb_config->SataIdeMode = SATA_IDE_MODE; - sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED; - sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER; - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. - //TODO: set to secondary not take effect. - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CONFIG_IDE_COMBINED_MODE; - sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE; - - /* Azalia HDA */ - sb_config->AzaliaController = AZALIA_CONTROLLER; - sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; - sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN; - /* Mainboard Specific Azalia Codec Verb Table */ -#ifdef AZALIA_OEM_VERB_TABLE - sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = (CODECTBLLIST *)AZALIA_OEM_VERB_TABLE; -#else - sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL; -#endif - /* LPC */ - /* SuperIO hardware monitor register access */ - sb_config->SioHwmPortEnable = CONFIG(SB_SUPERIO_HWM); - - /* - * GPP. default configure only enable port0 with 4 lanes, - * configure in devicetree.cb would overwrite the default configuration - */ - sb_config->GppFunctionEnable = GPP_CONTROLLER; - sb_config->GppLinkConfig = GPP_CFGMODE; - //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE; - sb_config->PORTCONFIG[0].PortCfg.PortPresent = CIMX_OPTION_ENABLED; - sb_config->PORTCONFIG[1].PortCfg.PortPresent = CIMX_OPTION_ENABLED; - sb_config->PORTCONFIG[2].PortCfg.PortPresent = CIMX_OPTION_ENABLED; - sb_config->PORTCONFIG[3].PortCfg.PortPresent = CIMX_OPTION_ENABLED; - sb_config->GppUnhidePorts = SB_GPP_UNHIDE_PORTS; - sb_config->NbSbGen2 = NB_SB_GEN2; - sb_config->GppGen2 = SB_GPP_GEN2; - - //cimx BTS fix - sb_config->GppMemWrImprove = TRUE; - sb_config->SbPcieOrderRule = TRUE; - sb_config->AlinkPhyPllPowerDown = TRUE; - sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving - sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06 - sb_config->GecConfig = GEC_CONFIG; -} diff --git a/src/southbridge/amd/cimx/sb800/cfg.h b/src/southbridge/amd/cimx/sb800/cfg.h deleted file mode 100644 index 25b2a45cab..0000000000 --- a/src/southbridge/amd/cimx/sb800/cfg.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SB800_CFG_H_ -#define _SB800_CFG_H_ - -/** - * @brief South Bridge CIMx configuration - * - */ -void sb800_cimx_config(AMDSBCFG *sb_cfg); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/chip.h b/src/southbridge/amd/cimx/sb800/chip.h deleted file mode 100644 index 48c9622aef..0000000000 --- a/src/southbridge/amd/cimx/sb800/chip.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _CIMX_SB800_CHIP_H_ -#define _CIMX_SB800_CHIP_H_ -#include "fan.h" /* include for #defines used in devicetree.cb */ - -/* - * configuration set in mainboard/devicetree.cb - * boot_switch_sata_ide: - * 0 -set SATA as primary, PATA(IDE) as secondary. - * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE, - * gpp_configuration - The configuration of General Purpose Port A/B/C/D - * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0] - * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2] - * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3 - * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 - */ -struct southbridge_amd_cimx_sb800_config -{ - u32 boot_switch_sata_ide : 1; - u32 disconnect_pcib : 1; - u8 gpp_configuration; - - /* - * SB800 IMC and fan control - */ - - u16 imc_port_address; - - u32 fan0_enabled : 1; - u32 fan1_enabled : 1; - u32 fan2_enabled : 1; - u32 fan3_enabled : 1; - u32 fan4_enabled : 1; - u32 imc_fan_zone0_enabled : 1; - u32 imc_fan_zone1_enabled : 1; - u32 imc_fan_zone2_enabled : 1; - u32 imc_fan_zone3_enabled : 1; - u32 imc_tempin0_enabled : 1; - u32 imc_tempin1_enabled : 1; - u32 imc_tempin2_enabled : 1; - u32 imc_tempin3_enabled : 1; - - union { - struct { - u8 fan0_control_reg_value; - u8 fan0_frequency_reg_value; - u8 fan0_low_duty_reg_value; - u8 fan0_med_duty_reg_value; - u8 fan0_multiplier_reg_value; - u8 fan0_low_temp_lo_reg_value; - u8 fan0_low_temp_hi_reg_value; - u8 fan0_med_temp_lo_reg_value; - u8 fan0_med_temp_hi_reg_value; - u8 fan0_high_temp_lo_reg_value; - u8 fan0_high_temp_hi_reg_value; - u8 fan0_linear_range_reg_value; - u8 fan0_linear_hold_reg_value; - }; - u8 fan0_config_vals[FAN_REGISTER_COUNT]; - }; - - union { - struct { - u8 fan1_control_reg_value; - u8 fan1_frequency_reg_value; - u8 fan1_low_duty_reg_value; - u8 fan1_med_duty_reg_value; - u8 fan1_multiplier_reg_value; - u8 fan1_low_temp_lo_reg_value; - u8 fan1_low_temp_hi_reg_value; - u8 fan1_med_temp_lo_reg_value; - u8 fan1_med_temp_hi_reg_value; - u8 fan1_high_temp_lo_reg_value; - u8 fan1_high_temp_hi_reg_value; - u8 fan1_linear_range_reg_value; - u8 fan1_linear_hold_reg_value; - }; - u8 fan1_config_vals[FAN_REGISTER_COUNT]; - }; - - union { - struct { - u8 fan2_control_reg_value; - u8 fan2_frequency_reg_value; - u8 fan2_low_duty_reg_value; - u8 fan2_med_duty_reg_value; - u8 fan2_multiplier_reg_value; - u8 fan2_low_temp_lo_reg_value; - u8 fan2_low_temp_hi_reg_value; - u8 fan2_med_temp_lo_reg_value; - u8 fan2_med_temp_hi_reg_value; - u8 fan2_high_temp_lo_reg_value; - u8 fan2_high_temp_hi_reg_value; - u8 fan2_linear_range_reg_value; - u8 fan2_linear_hold_reg_value; - }; - u8 fan2_config_vals[FAN_REGISTER_COUNT]; - }; - - union { - struct { - u8 fan3_control_reg_value; - u8 fan3_frequency_reg_value; - u8 fan3_low_duty_reg_value; - u8 fan3_med_duty_reg_value; - u8 fan3_multiplier_reg_value; - u8 fan3_low_temp_lo_reg_value; - u8 fan3_low_temp_hi_reg_value; - u8 fan3_med_temp_lo_reg_value; - u8 fan3_med_temp_hi_reg_value; - u8 fan3_high_temp_lo_reg_value; - u8 fan3_high_temp_hi_reg_value; - u8 fan3_linear_range_reg_value; - u8 fan3_linear_hold_reg_value; - }; - u8 fan3_config_vals[FAN_REGISTER_COUNT]; - }; - - union { - struct { - u8 fan4_control_reg_value; - u8 fan4_frequency_reg_value; - u8 fan4_low_duty_reg_value; - u8 fan4_med_duty_reg_value; - u8 fan4_multiplier_reg_value; - u8 fan4_low_temp_lo_reg_value; - u8 fan4_low_temp_hi_reg_value; - u8 fan4_med_temp_lo_reg_value; - u8 fan4_med_temp_hi_reg_value; - u8 fan4_high_temp_lo_reg_value; - u8 fan4_high_temp_hi_reg_value; - u8 fan4_linear_range_reg_value; - u8 fan4_linear_hold_reg_value; - }; - u8 fan4_config_vals[FAN_REGISTER_COUNT]; - }; - - union { - struct { - u8 imc_zone0_mode1; - u8 imc_zone0_mode2; - u8 imc_zone0_temp_offset; - u8 imc_zone0_hysteresis; - u8 imc_zone0_smbus_addr; - u8 imc_zone0_smbus_num; - u8 imc_zone0_pwm_step; - u8 imc_zone0_ramping; - }; - u8 imc_zone0_config_vals[IMC_FAN_CONFIG_COUNT]; - }; - u8 imc_zone0_thresholds[IMC_FAN_THRESHOLD_COUNT]; - u8 imc_zone0_fanspeeds[IMC_FAN_SPEED_COUNT]; - - union { - struct { - u8 imc_zone1_mode1; - u8 imc_zone1_mode2; - u8 imc_zone1_temp_offset; - u8 imc_zone1_hysteresis; - u8 imc_zone1_smbus_addr; - u8 imc_zone1_smbus_num; - u8 imc_zone1_pwm_step; - u8 imc_zone1_ramping; - }; - u8 imc_zone1_config_vals[IMC_FAN_CONFIG_COUNT]; - }; - u8 imc_zone1_thresholds[IMC_FAN_THRESHOLD_COUNT]; - u8 imc_zone1_fanspeeds[IMC_FAN_SPEED_COUNT]; - - union { - struct { - u8 imc_zone2_mode1; - u8 imc_zone2_mode2; - u8 imc_zone2_temp_offset; - u8 imc_zone2_hysteresis; - u8 imc_zone2_smbus_addr; - u8 imc_zone2_smbus_num; - u8 imc_zone2_pwm_step; - u8 imc_zone2_ramping; - }; - u8 imc_zone2_config_vals[IMC_FAN_CONFIG_COUNT]; - }; - u8 imc_zone2_thresholds[IMC_FAN_THRESHOLD_COUNT]; - u8 imc_zone2_fanspeeds[IMC_FAN_SPEED_COUNT]; - - union { - struct { - u8 imc_zone3_mode1; - u8 imc_zone3_mode2; - u8 imc_zone3_temp_offset; - u8 imc_zone3_hysteresis; - u8 imc_zone3_smbus_addr; - u8 imc_zone3_smbus_num; - u8 imc_zone3_pwm_step; - u8 imc_zone3_ramping; - }; - u8 imc_zone3_config_vals[IMC_FAN_CONFIG_COUNT]; - }; - u8 imc_zone3_thresholds[IMC_FAN_THRESHOLD_COUNT]; - u8 imc_zone3_fanspeeds[IMC_FAN_SPEED_COUNT]; - - u32 imc_tempin0_at; - u32 imc_tempin0_ct; - u8 imc_tempin0_tuning_param; - - u32 imc_tempin1_at; - u32 imc_tempin1_ct; - u8 imc_tempin1_tuning_param; - - u32 imc_tempin2_at; - u32 imc_tempin2_ct; - u8 imc_tempin2_tuning_param; - - u32 imc_tempin3_at; - u32 imc_tempin3_ct; - u8 imc_tempin3_tuning_param; - -}; -#endif /* _CIMX_SB800_CHIP_H_ */ diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c deleted file mode 100644 index 7ea179c94e..0000000000 --- a/src/southbridge/amd/cimx/sb800/early.c +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include "SBPLATFORM.h" -#include "sb_cimx.h" -#include "cfg.h" /*sb800_cimx_config*/ - -/** - * @brief South Bridge CIMx romstage entry, - * wrapper of sbPowerOnInit entry point. - */ -void sb_Poweron_Init(void) -{ - AMDSBCFG sb_early_cfg; - - sb800_cimx_config(&sb_early_cfg); - //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT; - //AmdSbDispatcher(&sb_early_cfg); - //TODO - //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher, - // VerifyImage() will fail, LocateImage() takes minutes to find the image. - sbPowerOnInit(&sb_early_cfg); -} - -/** - * CIMX not set the clock to 48Mhz until sbBeforePciInit, - * coreboot may need to set this even more earlier - */ -void sb800_clk_output_48Mhz(void) -{ - - misc_write32(0x40, misc_read32(0x40) & (~5)); - misc_write32(0x40, misc_read32(0x40) | 2); -} diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c deleted file mode 100644 index b4ea285ed7..0000000000 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * ACPI - create the Fixed ACPI Description Tables (FADT) - */ - -#include <console/console.h> -#include <acpi/acpi.h> -#include <arch/io.h> -#include <device/device.h> -#include <version.h> - -#include "SBPLATFORM.h" - -#ifndef FADT_BOOT_ARCH -#if LEGACY_FREE - #define FADT_BOOT_ARCH ACPI_FADT_LEGACY_FREE -#else - #define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) -#endif -#endif - -/* - * Reference section 5.2.9 Fixed ACPI Description Table (FADT) - * in the ACPI 3.0b specification. - */ -void acpi_fill_fadt(acpi_fadt_t *fadt) -{ - u16 val = 0; - - printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); - - fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 - ACPI SCI */ - - val = PM1_EVT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG60, AccWidthUint16, &val); - val = PM1_CNT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG62, AccWidthUint16, &val); - val = PM1_TMR_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG64, AccWidthUint16, &val); - val = GPE0_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG68, AccWidthUint16, &val); - - /* CpuControl is in \_PR.CP00, 6 bytes */ - val = CPU_CNT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG66, AccWidthUint16, &val); - val = 0; - WritePMIO(SB_PMIOA_REG6A, AccWidthUint16, &val); - val = ACPI_PMA_CNT_BLK_ADDRESS; - WritePMIO(SB_PMIOA_REG6E, AccWidthUint16, &val); - - /* AcpiDecodeEnable, When set, SB uses the contents of the - * PM registers at index 60-6B to decode ACPI I/O address. - * AcpiSmiEn & SmiCmdEn*/ - val = BIT0 | BIT1 | BIT2 | BIT4; - WritePMIO(SB_PMIOA_REG74, AccWidthUint16, &val); - - /* RTC_En_En, TMR_En_En, GBL_EN_EN */ - outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ - fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; - fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; - fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; - fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; - fadt->gpe0_blk = GPE0_BLK_ADDRESS; - - fadt->pm1_evt_len = 4; /* 32 bits */ - fadt->pm1_cnt_len = 2; /* 16 bits */ - fadt->pm2_cnt_len = 1; /* 8 bits */ - fadt->pm_tmr_len = 4; /* 32 bits */ - fadt->gpe0_blk_len = 8; /* 64 bits */ - - fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; - fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; - fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ - fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ - fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_S4_RTC_VALID | - ACPI_FADT_REMOTE_POWER_ON; - - fadt->ARM_boot_arch = 0; /* Must be zero if ACPI Revision <= 5.0 */ - - fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; - fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; - fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; - fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; - fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; /* EventStatus + Event Enable */ - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; - fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; - fadt->x_gpe0_blk.addrh = 0x0; -} diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c deleted file mode 100644 index f5e0a48f4d..0000000000 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ /dev/null @@ -1,283 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <device/device.h> -#include <device/pci.h> /* device_operations */ -#include <device/pci_ops.h> -#include "SBPLATFORM.h" -#include "sb_cimx.h" -#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ -#include "fan.h" - -void init_sb800_MANUAL_fans(struct device *dev) -{ - int i; - struct southbridge_amd_cimx_sb800_config *sb_chip = - (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); - - /* Init Fan 0 */ - if (sb_chip->fan0_enabled) - for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_write8(FAN_0_OFFSET + i, sb_chip->fan0_config_vals[i]); - - /* Init Fan 1 */ - if (sb_chip->fan1_enabled) - for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_write8(FAN_1_OFFSET + i, sb_chip->fan1_config_vals[i]); - - /* Init Fan 2 */ - if (sb_chip->fan2_enabled) - for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_write8(FAN_2_OFFSET + i, sb_chip->fan2_config_vals[i]); - - /* Init Fan 3 */ - if (sb_chip->fan3_enabled) - for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_write8(FAN_3_OFFSET + i, sb_chip->fan3_config_vals[i]); - - /* Init Fan 4 */ - if (sb_chip->fan4_enabled) - for (i = 0; i < FAN_REGISTER_COUNT; i++) - pm2_write8(FAN_4_OFFSET + i, sb_chip->fan4_config_vals[i]); -} - -void init_sb800_IMC_fans(struct device *dev) -{ - AMDSBCFG sb_config; - unsigned char *message_ptr; - int i; - struct southbridge_amd_cimx_sb800_config *sb_chip = - (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); - - /* - * The default I/O address of the IMC configuration register index - * port is 0x6E. Change the IMC Config port I/O Address if it - * conflicts with other components in the system. - * - * Device 20, Function 3, Reg 0xA4 - * [0]: if 1, the address specified in IMC_PortAddress is used. - * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E) - */ - - pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01); - - /* - * Do an initial manual setup of the fans for things like polarity - * and frequency. - */ - init_sb800_MANUAL_fans(dev); - - /* - * FLAG for Func 81/83/85/89 support (1=On,0=Off) - * Bit0-3 = Func 81 Zone0-Zone3 - * Bit4-7 = Func 83 Zone0-Zone3 - * Bit8-11 = Func 85 Zone0-Zone3 - * Bit12-15 = Func 89 Tempin Channel0-Channel3 - */ - sb_config.Pecstruct.IMCFUNSupportBitMap = 0; - -/* - ********** Zone 0 ********** - */ -if (sb_chip->imc_fan_zone0_enabled) { - - sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE0; - - /* EC LDN9 function 81 zone 0 */ - sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; - message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; - - /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ - sb_config.Pecstruct.MSGFun83zone0MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; - sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; - message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; - - /*EC LDN9 function 85 zone 0 - Fan Speeds */ - sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; - message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; -} - -/* - ********** Zone 1 ********** - */ -if (sb_chip->imc_fan_zone1_enabled) { - - sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE1; - - /* EC LDN9 function 81 zone 1 */ - sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; - message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; - - /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ - sb_config.Pecstruct.MSGFun83zone1MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; - sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; - message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; - - /* EC LDN9 function 85 zone 1 - Fan Speeds */ - sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; - message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; -} - -/* - ********** Zone 2 ********** - */ -if (sb_chip->imc_fan_zone2_enabled) { - - sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE2; - - /* EC LDN9 function 81 zone 2 */ - sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; - message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; - - /* EC LDN9 function 83 zone 2 */ - sb_config.Pecstruct.MSGFun83zone2MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; - sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; - message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; - - /* EC LDN9 function 85 zone 2 */ - sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; - message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; -} - -/* - ********** Zone 3 ********** - */ - -if (sb_chip->imc_fan_zone3_enabled) { - - sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_ZONE3; - - /* EC LDN9 function 81 zone 3 */ - sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; - message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; - - /* EC LDN9 function 83 zone 3 */ - sb_config.Pecstruct.MSGFun83zone3MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; - sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; - message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; - - /* EC LDN9 function 85 zone 3 */ - sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; - message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) - *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; -} - - /* - * EC LDN9 function 89 - Set HWM TEMPIN Temperature Calculation Parameters - * This function provides the critical parameters of the HWM TempIn - * sensors, IMC would not perform temperature measurement using those - * sensors until the parameters are provided. - */ - -if (sb_chip->imc_tempin0_enabled) { - - sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN0; - - /* EC LDN9 function 89 TEMPIN channel 0 */ - sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00; - sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREG3 = ((sb_chip->imc_tempin0_at >> 8) & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREG4 = ((sb_chip->imc_tempin0_at >> 16) & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREG5 = ((sb_chip->imc_tempin0_at >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREG7 = ((sb_chip->imc_tempin0_ct >> 8) & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREG8 = ((sb_chip->imc_tempin0_ct >> 16) & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREG9 = ((sb_chip->imc_tempin0_ct >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREGA = sb_chip->imc_tempin0_tuning_param; -} - -if (sb_chip->imc_tempin1_enabled) { - - sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN1; - - /* EC LDN9 function 89 TEMPIN channel 1 */ - sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01; - sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREG3 = ((sb_chip->imc_tempin1_at >> 8) & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREG4 = ((sb_chip->imc_tempin1_at >> 16) & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREG5 = ((sb_chip->imc_tempin1_at >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREG7 = ((sb_chip->imc_tempin1_ct >> 8) & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREG8 = ((sb_chip->imc_tempin1_ct >> 16) & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREG9 = ((sb_chip->imc_tempin1_ct >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREGA = sb_chip->imc_tempin1_tuning_param; -} - -if (sb_chip->imc_tempin2_enabled) { - - sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN2; - - /* EC LDN9 function 89 TEMPIN channel 2 */ - sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02; - sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREG3 = ((sb_chip->imc_tempin2_at >> 8) & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREG4 = ((sb_chip->imc_tempin2_at >> 16) & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREG5 = ((sb_chip->imc_tempin2_at >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREG7 = ((sb_chip->imc_tempin2_ct >> 8) & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREG8 = ((sb_chip->imc_tempin2_ct >> 16) & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREG9 = ((sb_chip->imc_tempin2_ct >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREGA = sb_chip->imc_tempin2_tuning_param; -} - -if (sb_chip->imc_tempin3_enabled) { - - sb_config.Pecstruct.IMCFUNSupportBitMap |= IMC_ENABLE_TEMPIN3; - - /* EC LDN9 function 89 TEMPIN channel 3 */ - sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00; - sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03; - sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREG3 = ((sb_chip->imc_tempin3_at >> 8) & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREG4 = ((sb_chip->imc_tempin3_at >> 16) & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREG5 = ((sb_chip->imc_tempin3_at >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREG7 = ((sb_chip->imc_tempin3_ct >> 8) & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREG8 = ((sb_chip->imc_tempin3_ct >> 16) & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREG9 = ((sb_chip->imc_tempin3_ct >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREGA = sb_chip->imc_tempin3_tuning_param; -} - - /* Set up the sb_config structure for the fan control initialization */ - sb_config.StdHeader.Func = SB_EC_FANCONTROL; - - AmdSbDispatcher(&sb_config); -} diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h deleted file mode 100644 index 9b763a5877..0000000000 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SB800_FAN_H_ -#define _SB800_FAN_H_ - -#include <device/device.h> - -void init_sb800_IMC_fans(struct device *dev); -void init_sb800_MANUAL_fans(struct device *dev); - -/* Fan Register Definitions */ -#define FAN_0_OFFSET 0x00 -#define FAN_1_OFFSET 0x10 -#define FAN_2_OFFSET 0x20 -#define FAN_3_OFFSET 0x30 -#define FAN_4_OFFSET 0x40 - -#define FAN_INPUT_CONTROL_REG 0x00 -#define FAN_CONTROL_REG 0x01 -#define FAN_FREQUENCY_REG 0x02 -#define FAN_LOW_DUTY_REG 0x03 -#define FAN_MED_DUTY_REG 0x04 -#define FAN_MULTIPLIER_REG 0x05 -#define FAN_LOW_TEMP_LO_REG 0x06 -#define FAN_LOW_TEMP_HI_REG 0x07 -#define FAN_MED_TEMP_LO_REG 0x08 -#define FAN_MED_TEMP_HI_REG 0x09 -#define FAN_HIGH_TEMP_LO_REG 0x0A -#define FAN_HIGH_TEMP_HI_REG 0x0B -#define FAN_LINEAR_RANGE_REG 0x0C -#define FAN_LINEAR_HOLD_REG 0x0D - -/* FanXInputControl Definitions */ -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -/* FanXControl Definitions */ -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE 0 /* ~(1 << 1) */ -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW 0 /*~(1 << 2) */ - -/* FanXLowDuty Definitions */ -#define FAN_POLARITY_HIGH_MAX_SPEED 0xff -#define FAN_POLARITY_LOW_MAX_SPEED 0x00 - -/* FanXFreq Definitions */ -/* Typically, fans run at 25KHz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -/* Any value > 05h and < F7: Freq = 1/(FreqDiv * 2048 * 15ns) */ -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* IMC Fan Control Definitions */ -#define IMC_MODE1_FAN_ENABLED (1 << 0) -#define IMC_MODE1_FAN_IMC_CONTROLLED (1 << 2) -#define IMC_MODE1_FAN_LINEAR_MODE (1 << 4) -#define IMC_MODE1_FAN_STEP_MODE 0 /* ~( 1 << 4 ) */ -#define IMC_MODE1_NO_FANOUT 0 /* ~( 7 << 5 ) */ -#define IMC_MODE1_FANOUT0 (1 << 5) -#define IMC_MODE1_FANOUT1 (2 << 5) -#define IMC_MODE1_FANOUT2 (3 << 5) -#define IMC_MODE1_FANOUT3 (4 << 5) -#define IMC_MODE1_FANOUT4 (5 << 5) - -#define IMC_MODE2_TEMPIN_NONE 0 /* ~( 7 << 0) */ -#define IMC_MODE2_TEMPIN_0 1 -#define IMC_MODE2_TEMPIN_1 2 -#define IMC_MODE2_TEMPIN_2 3 -#define IMC_MODE2_TEMPIN_3 4 -#define IMC_MODE2_INT_TEMPIN 5 -#define IMC_MODE2_TEMPIN_SB_TSI 6 -#define IMC_MODE2_TEMPIN_OTHER 7 -#define IMC_MODE2_FANIN_NONE 0 /* ~ (7 << 3) */ -#define IMC_MODE2_FANIN0 (1 << 3) -#define IMC_MODE2_FANIN1 (2 << 3) -#define IMC_MODE2_FANIN2 (3 << 3) -#define IMC_MODE2_FANIN3 (4 << 3) -#define IMC_MODE2_FANIN4 (5 << 3) -#define IMC_MODE2_TEMP_AVERAGING_ENABLED (1 << 6) -#define IMC_MODE2_TEMP_AVERAGING_DISABLED 0 /* ~( 1 << 6 ) */ - -#define IMC_TEMP_SENSOR_ON_SMBUS_0 0 -#define IMC_TEMP_SENSOR_ON_SMBUS_2 1 -#define IMC_TEMP_SENSOR_ON_SMBUS_3 2 -#define IMC_TEMP_SENSOR_ON_SMBUS_4 3 - -#define IMC_ZONE0 0 -#define IMC_ZONE1 1 -#define IMC_ZONE2 2 -#define IMC_ZONE3 3 -#define IMC_ZONE4 4 - -#define IMC_TEMPIN_TUNING_DEFAULT_MODE 0 -#define IMC_TEMPIN_TUNING_HIGH_CURRENT_RATIO 1 -#define IMC_TEMPIN_TUNING_HIGH_CURRENT 2 -#define IMC_TEMPIN_TUNING_DISABLE_FILTERING (1 << 2) - -/* IMCFUNSupportBitMap - Zone enable values */ -#define IMC_ENABLE_ZONE0 0x111 -#define IMC_ENABLE_ZONE1 0x222 -#define IMC_ENABLE_ZONE2 0x333 -#define IMC_ENABLE_ZONE3 0x444 -#define IMC_ENABLE_TEMPIN0 (1 << 12) -#define IMC_ENABLE_TEMPIN1 (1 << 13) -#define IMC_ENABLE_TEMPIN2 (1 << 14) -#define IMC_ENABLE_TEMPIN3 (1 << 15) - -/* Array size settings */ -#define IMC_FAN_THRESHOLD_COUNT 9 -#define IMC_FAN_SPEED_COUNT 8 -#define IMC_FAN_CONFIG_COUNT 8 -#define FAN_REGISTER_COUNT 15 - -#endif diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h deleted file mode 100644 index f61db5a6bf..0000000000 --- a/src/southbridge/amd/cimx/sb800/gpio_oem.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _CIMX_SB_GPIO_OEM_H_ -#define _CIMX_SB_GPIO_OEM_H_ - -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 - -/* FCH GPIO access helpers */ -#define FCH_IOMUX(gpio_nr) (*(u8 *)((uintptr_t)ACPI_MMIO_BASE + IOMUX_BASE + (gpio_nr))) -#define FCH_PMIO(reg_nr) (*(u8 *)((uintptr_t)ACPI_MMIO_BASE + PMIO_BASE + (reg_nr))) -#define FCH_GPIO(gpio_nr) (*(volatile u8 *)((uintptr_t)ACPI_MMIO_BASE + GPIO_BASE + (gpio_nr))) - -static inline u8 fch_gpio_state(unsigned int gpio_nr) -{ - return FCH_GPIO(gpio_nr) >> 7; -} - -#endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c deleted file mode 100644 index 88e426a1c5..0000000000 --- a/src/southbridge/amd/cimx/sb800/late.c +++ /dev/null @@ -1,439 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <amdblocks/acpimmio.h> -#include <device/mmio.h> -#include <device/device.h> -#include <device/pci.h> /* device_operations */ -#include <device/pci_ops.h> -#include <device/pci_ids.h> -#include <bootstate.h> -#include <arch/ioapic.h> -#include <device/smbus.h> /* smbus_bus_operations */ -#include <pc80/mc146818rtc.h> -#include <pc80/i8254.h> -#include <pc80/i8259.h> -#include <console/console.h> /* printk */ -#include <acpi/acpi.h> -#include <device/pci_ehci.h> -#include "lpc.h" /* lpc_read_resources */ -#include "SBPLATFORM.h" /* Platform Specific Definitions */ -#include "cfg.h" /* sb800 Cimx configuration */ -#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ -#include "sb_cimx.h" /* AMD CIMX wrapper entries */ -#include "smbus.h" -#include "fan.h" -#include "pci_devs.h" -#include <southbridge/amd/common/amd_pci_util.h> - -static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config -static AMDSBCFG *sb_config = &sb_late_cfg; - -/** - * @brief Entry point of Southbridge CIMx callout - * - * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) - * - * @param[in] func Southbridge CIMx Function ID. - * @param[in] data Southbridge Input Data. - * @param[in] config Southbridge configuration structure pointer. - * - */ -static u32 sb800_callout_entry(u32 func, u32 data, void *config) -{ - u32 ret = 0; - printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); - switch (func) { - case CB_SBGPP_RESET_ASSERT: - break; - - case CB_SBGPP_RESET_DEASSERT: - break; - - case IMC_FIRMWARE_FAIL: - break; - - default: - break; - } - - printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); - return ret; -} - -#define HOST_CAP 0x00 /* host capabilities */ -#define HOST_CTL 0x04 /* global host control */ -#define HOST_IRQ_STAT 0x08 /* interrupt status */ -#define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ - -#define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ -static void ahci_raid_init(struct device *dev) -{ - u8 irq = 0; - void *bar5; - u32 caps, ports, val; - - val = pci_read_config16(dev, PCI_CLASS_DEVICE); - if (val == PCI_CLASS_STORAGE_SATA) { - printk(BIOS_DEBUG, "AHCI controller "); - } else if (val == PCI_CLASS_STORAGE_RAID) { - printk(BIOS_DEBUG, "RAID controller "); - } else { - printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); - return; - } - - irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); - bar5 = (void *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "IOMEM base: %p, IRQ: 0x%X\n", bar5, irq); - - caps = read32(bar5 + HOST_CAP); - caps = (caps & 0x1F) + 1; - ports = read32(bar5 + HOST_PORTS_IMPL); - printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); - - /* make sure ahci is enabled */ - val = read32(bar5 + HOST_CTL); - if (!(val & HOST_CTL_AHCI_EN)) { - write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN); - } - - dev->command |= PCI_COMMAND_MASTER; - pci_write_config8(dev, PCI_COMMAND, dev->command); - printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); -} - -static void lpc_init(struct device *dev) -{ - printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); - - cmos_check_update_date(); - - /* Initialize the real time clock. - * The 0 argument tells cmos_init not to - * update CMOS unless it is invalid. - * 1 tells cmos_init to always initialize the CMOS. - */ - cmos_init(0); - - setup_i8259(); /* Initialize i8259 pic */ - setup_i8254(); /* Initialize i8254 timers */ - - printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); -} - -static const char *lpc_acpi_name(const struct device *dev) -{ - if (dev->path.type != DEVICE_PATH_PCI) - return NULL; - - switch (dev->path.pci.devfn) { - /* DSDT: acpi/lpc.asl */ - case LPC_DEVFN: - return "LIBR"; - } - - return NULL; -} - -static struct device_operations lpc_ops = { - .read_resources = lpc_read_resources, - .set_resources = lpc_set_resources, - .enable_resources = pci_dev_enable_resources, -#if CONFIG(HAVE_ACPI_TABLES) - .write_acpi_tables = acpi_write_hpet, -#endif - .init = lpc_init, - .scan_bus = scan_static_bus, - .ops_pci = &pci_dev_ops_pci, - .acpi_name = lpc_acpi_name, -}; - -static const struct pci_driver lpc_driver __pci_driver = { - .ops = &lpc_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_LPC, -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ahci_raid_init, - .ops_pci = &pci_dev_ops_pci, -}; - -static const struct pci_driver ahci_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_SATA_AHCI, -}; - -static const struct pci_driver raid_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_SATA_RAID, -}; -static const struct pci_driver raid5_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_SATA_RAID5, -}; - -static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .ops_pci = &pci_dev_ops_pci, -}; - -/* - * The pci id of USB ctrl 0 and 1 are the same. - */ -static const struct pci_driver usb_ohci123_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ -}; - -static const struct pci_driver usb_ehci123_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ -}; - -static const struct pci_driver usb_ohci4_driver __pci_driver = { - .ops = &usb_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ -}; - -static struct device_operations azalia_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .ops_pci = &pci_dev_ops_pci, -}; - -static const struct pci_driver azalia_driver __pci_driver = { - .ops = &azalia_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_HDA, -}; - -static struct device_operations gec_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .ops_pci = &pci_dev_ops_pci, -}; - -static const struct pci_driver gec_driver __pci_driver = { - .ops = &gec_ops, - .vendor = PCI_VID_ATI, - .device = PCI_DID_ATI_SB800_GEC, -}; - -/** - * Fill build time defaults. - */ -static void sb800_init(void *chip_info) -{ - printk(BIOS_DEBUG, "SB800: %s\n", __func__); - sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; - sb800_cimx_config(sb_config); - - /* Initially enable all GPP ports 0 to 3 */ - abcfg_reg(0xc0, 0x01FF, 0x0F4); -} - -/** - * South Bridge CIMx ramstage entry point wrapper. - */ -void sb_Before_Pci_Init(void) -{ - printk(BIOS_DEBUG, "SB800: %s\n", __func__); - sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_After_Pci_Init(void) -{ - printk(BIOS_DEBUG, "SB800: %s\n", __func__); - sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Mid_Post_Init(void) -{ - printk(BIOS_DEBUG, "SB800: %s\n", __func__); - sb_config->StdHeader.Func = SB_MID_POST_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Late_Post(void) -{ - printk(BIOS_DEBUG, "SB800: %s\n", __func__); - sb_config->StdHeader.Func = SB_LATE_POST_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_Before_Pci_Restore_Init(void) -{ - printk(BIOS_DEBUG, "SB800: %s\n", __func__); - sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; - AmdSbDispatcher(sb_config); -} - -void sb_After_Pci_Restore_Init(void) -{ - printk(BIOS_DEBUG, "SB800: %s\n", __func__); - sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; - AmdSbDispatcher(sb_config); -} - -/* - * Update the PCI devices with a valid IRQ number - * that is set in the mainboard PCI_IRQ structures. - */ -static void set_pci_irqs(void *unused) -{ - /* Write PCI_INTR regs 0xC00/0xC01 */ - write_pci_int_table(); - - /* Write IRQs for all devicetree enabled devices */ - write_pci_cfg_irqs(); -} - -/* - * Hook this function into the PCI state machine - * on entry into BS_DEV_ENABLE. - */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); - -/** - * @brief SB Cimx entry point sbBeforePciInit wrapper - */ -static void sb800_enable(struct device *dev) -{ - struct southbridge_amd_cimx_sb800_config *sb_chip = - (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); - - switch (dev->path.pci.devfn) { - case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */ - if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; - if (sb_chip->boot_switch_sata_ide == 1) - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. - else if (sb_chip->boot_switch_sata_ide == 0) - sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. - } else { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; - } - break; - - case PCI_DEVFN(0x14, 0): /* 0:14:0 SMBUS */ - /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ - setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); - break; - - case PCI_DEVFN(0x14, 1): /* 0:14:1 IDE */ - break; - - case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */ - if (dev->enabled) { - if (sb_config->AzaliaController == AZALIA_DISABLE) { - sb_config->AzaliaController = AZALIA_AUTO; - } - } else { - sb_config->AzaliaController = AZALIA_DISABLE; - } - break; - - case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */ - /* Initialize the fans */ -#if CONFIG(SB800_IMC_FAN_CONTROL) - init_sb800_IMC_fans(dev); -#elif CONFIG(SB800_MANUAL_FAN_CONTROL) - init_sb800_MANUAL_fans(dev); -#endif - break; - - case PCI_DEVFN(0x14, 4): /* 0:14:4 PCI */ - /* PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] - * 'PCIDisable' set to 0 to enable P2P bridge. - * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins - * to function as GPIO {GPIO 35:0}. - */ - if (!sb_chip->disconnect_pcib && dev->enabled) - pm_write8(0xea, pm_read8(0xea) & 0xfe); - else - pm_write8(0xea, (pm_read8(0xea) & 0xfe) | 1); - break; - - case PCI_DEVFN(0x14, 6): /* 0:14:6 GEC */ - if (dev->enabled) { - sb_config->GecConfig = 0; - } else { - sb_config->GecConfig = 1; - } - break; - - case PCI_DEVFN(0x15, 0): /* 0:15:0 PCIe PortA */ - { - struct device *device; - for (device = dev; device; device = device->sibling) { - if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15, 0)) break; - sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; - } - - /* - * GPP_CFGMODE_X4000: PortA Lanes[3:0] - * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] - * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 - * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 - */ - sb_config->GppLinkConfig = sb_chip->gpp_configuration; - } - break; - - case PCI_DEVFN(0x12, 0): /* 0:12:0 OHCI-USB1 */ - sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; - break; - case PCI_DEVFN(0x12, 2): /* 0:12:2 EHCI-USB1 */ - sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; - break; - case PCI_DEVFN(0x13, 0): /* 0:13:0 OHCI-USB2 */ - sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; - break; - case PCI_DEVFN(0x13, 2): /* 0:13:2 EHCI-USB2 */ - sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; - break; - case PCI_DEVFN(0x14, 5): /* 0:14:5 OHCI-USB4 */ - sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; - break; - case PCI_DEVFN(0x16, 0): /* 0:16:0 OHCI-USB3 */ - sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; - break; - case PCI_DEVFN(0x16, 2): /* 0:16:2 EHCI-USB3 */ - sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; - - /* FIXME: Find better callsites for these. - * call the CIMX entry at the last sb800 device, - * so make sure the mainboard devicetree is complete - */ - if (!acpi_is_wakeup_s3()) - sb_Before_Pci_Init(); - else - sb_Before_Pci_Restore_Init(); - break; - - default: - break; - } -} - -struct chip_operations southbridge_amd_cimx_sb800_ops = { - CHIP_NAME("ATI SB800") - .init = sb800_init, - .enable_dev = sb800_enable, -}; diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c deleted file mode 100644 index 12a21d2f36..0000000000 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ /dev/null @@ -1,170 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <device/pci.h> -#include <device/pci_def.h> -#include <arch/ioapic.h> -#include "lpc.h" -#include <device/pci_ops.h> - -void lpc_read_resources(struct device *dev) -{ - struct resource *res; - - printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); - /* Get the normal pci resources of this device */ - pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ - - /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); - res->base = 0; - res->size = 0x1000; - res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = 0xff800000; - res->size = 0x00800000; /* 8 MB for flash */ - res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | - IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - /* Add a memory resource for the SPI BAR. */ - mmio_range(dev, 2, SPI_BASE_ADDRESS, 1 * KiB); - - res = new_resource(dev, 3); - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - - compact_resources(dev); - printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); -} - -void lpc_set_resources(struct device *dev) -{ - struct resource *res; - - printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); - - /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ - res = find_resource(dev, 2); - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); - - pci_dev_set_resources(dev); - - printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); -} - -/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -void lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_x; - int var_num = 0; - u16 reg_var[3]; - - printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - Start.\n", __func__); - reg = pci_read_config32(dev, 0x44); - reg_x = pci_read_config32(dev, 0x48); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) { - struct resource *res; - for (res = child->resource_list; res; res = res->next) { - u32 base; /* don't need long long */ - if (!(res->flags & IORESOURCE_IO)) - continue; - base = res->base; -/* - printk(BIOS_DEBUG, "sb800 lpc decode:%s, - base=0x%08x, end=0x%08x\n", - dev_path(child), base, - resource_end(res)); -*/ - switch (base) { - case 0x60: /* KB */ - case 0x64: /* MS */ - reg |= (1 << 29); - break; - case 0x3f8: /* COM1 */ - reg |= (1 << 6); - break; - case 0x2f8: /* COM2 */ - reg |= (1 << 7); - break; - case 0x378: /* Parallel 1 */ - reg |= (1 << 0); - break; - case 0x3f0: /* FD0 */ - reg |= (1 << 26); - break; - case 0x220: /* Audio 0 */ - reg |= (1 << 8); - break; - case 0x300: /* Midi 0 */ - reg |= (1 << 18); - break; - case 0x400: - reg_x |= (1 << 16); - break; - case 0x480: - reg_x |= (1 << 17); - break; - case 0x500: - reg_x |= (1 << 18); - break; - case 0x580: - reg_x |= (1 << 19); - break; - case 0x4700: - reg_x |= (1 << 22); - break; - case 0xfd60: - reg_x |= (1 << 23); - break; - default: - if (var_num >= 3) - continue; /* only 3 var ; compact them ? */ - switch (var_num) { - case 0: - reg_x |= (1 << 2); - break; - case 1: - reg_x |= (1 << 24); - break; - case 2: - reg_x |= (1 << 25); - break; - } - reg_var[var_num++] = - base & 0xffff; - } - } - } - } - } - pci_write_config32(dev, 0x44, reg); - pci_write_config32(dev, 0x48, reg_x); - /* Set WideIO for as many IOs found (fall through is on purpose) */ - switch (var_num) { - case 3: - pci_write_config16(dev, 0x90, reg_var[2]); - __fallthrough; - case 2: - pci_write_config16(dev, 0x66, reg_var[1]); - __fallthrough; - case 1: - //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata - break; - } - printk(BIOS_DEBUG, "SB800 - Lpc.c - %s - End.\n", __func__); -} diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h deleted file mode 100644 index 809ff7fd4e..0000000000 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SB800_LPC_H_ -#define _SB800_LPC_H_ - -#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 -#define SPI_ROM_ENABLE 0x02 -#define SPI_BASE_ADDRESS 0xFEC10000 - -void lpc_read_resources(struct device *dev); -void lpc_set_resources(struct device *dev); -void lpc_enable_childrens_resources(struct device *dev); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/pci_devs.h b/src/southbridge/amd/cimx/sb800/pci_devs.h deleted file mode 100644 index 91825ba16e..0000000000 --- a/src/southbridge/amd/cimx/sb800/pci_devs.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _CIMX_SB800_PCI_DEVS_H_ -#define _CIMX_SB800_PCI_DEVS_H_ - -#include <device/pci_def.h> - -#define BUS0 0 - -/* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x4390 -#define AHCI_DEVID 0x4391 -#define RAID_DEVID 0x4392 -#define RAID5_DEVID 0x4393 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) - -/* OHCI */ -#define OHCI1_DEV 0x12 -#define OHCI1_FUNC 0 -#define OHCI2_DEV 0x13 -#define OHCI2_FUNC 0 -#define OHCI3_DEV 0x16 -#define OHCI3_FUNC 0 -#define OHCI4_DEV 0x14 -#define OHCI4_FUNC 5 -#define OHCI_DEVID 0x4397 -#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC) -#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC) -#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC) -#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC) - -/* EHCI */ -#define EHCI1_DEV 0x12 -#define EHCI1_FUNC 2 -#define EHCI2_DEV 0x13 -#define EHCI2_FUNC 2 -#define EHCI3_DEV 0x16 -#define EHCI3_FUNC 2 -#define EHCI_DEVID 0x4396 -#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC) -#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC) -#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC) - -/* Fusion Controller Hub */ -#define SMBUS_DEV 0x14 -#define SMBUS_FUNC 0 -#define SMBUS_DEVID 0x4385 -#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) - -/* IDE */ -#define IDE_DEV 0x14 -#define IDE_FUNC 1 -#define IDE_DEVID 0x439C -#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC) - -/* HD Audio */ -#define HDA_DEV 0x14 -#define HDA_FUNC 2 -#define HDA_DEVID 0x4383 -#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC) - -/* LPC BUS */ -#define PCU_DEV 0x14 -#define LPC_DEV PCU_DEV -#define LPC_FUNC 3 -#define LPC_DEVID 0x439D -#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC) - -/* PCI Ports */ -#define SB_PCI_PORT_DEV 0x14 -#define SB_PCI_PORT_FUNC 4 -#define SB_PCI_PORT_DEVID 0x4384 -#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC) - -/* PCIe Ports */ -#define SB_PCIE_DEV 0x15 -#define SB_PCIE_PORT1_FUNC 0 -#define SB_PCIE_PORT2_FUNC 1 -#define SB_PCIE_PORT3_FUNC 2 -#define SB_PCIE_PORT4_FUNC 3 -#define SB_PCIE_PORT1_DEVID 0x43A0 -#define SB_PCIE_PORT2_DEVID 0x43A1 -#define SB_PCIE_PORT3_DEVID 0x43A2 -#define SB_PCIE_PORT4_DEVID 0x43A3 -#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC) -#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC) -#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC) -#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC) - -#endif /* _CIMX_SB800_PCI_DEVS_H_ */ diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c deleted file mode 100644 index 483716c202..0000000000 --- a/src/southbridge/amd/cimx/sb800/ramtop.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/io.h> -#include <acpi/acpi.h> -#include "SBPLATFORM.h" - -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(PM1_CNT_BLK_ADDRESS); - tmp = ((tmp & (7 << 10)) >> 10); - return (int)tmp; -} diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c deleted file mode 100644 index 6c8f0e426c..0000000000 --- a/src/southbridge/amd/cimx/sb800/reset.c +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <device/pci_ops.h> -#include <cf9_reset.h> -#include <reset.h> - -#define HT_INIT_CONTROL 0x6c -#define HTIC_BIOSR_Detect (1 << 5) - -#define DEV_CDB 0x18 -#define NODE_PCI(x, fn) (((DEV_CDB + x) < 32) ? (PCI_DEV(0, (DEV_CDB + x), fn)) : (PCI_DEV((0 - 1), (DEV_CDB + x - 32), fn))) - -void cf9_reset_prepare(void) -{ - u32 nodes; - u32 htic; - pci_devfn_t dev; - int i; - - nodes = ((pci_read_config32(PCI_DEV(0, DEV_CDB, 0), 0x60) >> 4) & 7) + 1; - for (i = 0; i < nodes; i++) { - dev = NODE_PCI(i, 0); - htic = pci_read_config32(dev, HT_INIT_CONTROL); - htic &= ~HTIC_BIOSR_Detect; - pci_write_config32(dev, HT_INIT_CONTROL, htic); - } -} - -void do_board_reset(void) -{ - system_reset(); -} diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h deleted file mode 100644 index 5e5ca5d5f5..0000000000 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _CIMX_H_ -#define _CIMX_H_ - -/** - * AMD South Bridge CIMx entry point wrapper - */ -void sb_Poweron_Init(void); -void sb_Before_Pci_Init(void); -void sb_After_Pci_Init(void); -void sb_Mid_Post_Init(void); -void sb_Late_Post(void); -void sb_Before_Pci_Restore_Init(void); -void sb_After_Pci_Restore_Init(void); - -/** - * CIMX not set the clock to 48Mhz until sbBeforePciInit, - * coreboot may need to set this even more earlier - */ -void sb800_clk_output_48Mhz(void); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c deleted file mode 100644 index 50c77cf0b0..0000000000 --- a/src/southbridge/amd/cimx/sb800/smbus.c +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <stdint.h> -#include "smbus.h" -#include <console/console.h> - -static int smbus_wait_until_ready(u32 smbus_io_base) -{ - u32 loops; - - loops = SMBUS_TIMEOUT; - do { - u8 val; - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { /* ready now */ - return 0; - } - outb(val, smbus_io_base + SMBHSTSTAT); - } while (--loops); - - return -2; /* time out */ -} - -static int smbus_wait_until_done(u32 smbus_io_base) -{ - u32 loops; - - loops = SMBUS_TIMEOUT; - do { - u8 val; - - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; /* mask off reserved bits */ - if (val & 0x1c) { - return -5; /* error */ - } - if (val == 0x02) { - outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ - return 0; - } - } while (--loops); - - return -3; /* timeout */ -} - -int do_smbus_recv_byte(u32 smbus_io_base, u32 device) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__); - return -2; /* not ready */ - } - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTCMD); - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); - return byte; -} - -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__); - return -2; /* not ready */ - } - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); - /* set the command... */ - outb(val, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); - return 0; -} - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__); - return -2; /* not ready */ - } - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - /* read results of transaction */ - byte = inb(smbus_io_base + SMBHSTDAT0); - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); - return byte; -} - -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(smbus_io_base) < 0) { - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - smbus not ready.\n", __func__); - return -2; /* not ready */ - } - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); - /* set the command/address... */ - outb(address & 0xff, smbus_io_base + SMBHSTCMD); - - /* set the device I'm talking to */ - outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); - - /* output value */ - outb(val, smbus_io_base + SMBHSTDAT0); - - byte = inb(smbus_io_base + SMBHSTCTRL); - byte &= 0xe3; /* Clear [4:2] */ - byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ - outb(byte, smbus_io_base + SMBHSTCTRL); - - /* poll for transaction completion */ - if (smbus_wait_until_done(smbus_io_base) < 0) { - return -3; /* timeout or error */ - } - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); - return 0; -} - -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); -} - -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */ - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); -} - -/* space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) -{ - u32 tmp; - - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - Start.\n", __func__); - /* read axindc to tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); - printk(BIOS_DEBUG, "SB800 - smbus.c - %s - End.\n", __func__); -} diff --git a/src/southbridge/amd/cimx/sb800/smbus.h b/src/southbridge/amd/cimx/sb800/smbus.h deleted file mode 100644 index dfd55f87ea..0000000000 --- a/src/southbridge/amd/cimx/sb800/smbus.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SB800_SMBUS_H_ -#define _SB800_SMBUS_H_ - -#include <stdint.h> - -#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTRL 0x2 -#define SMBHSTCMD 0x3 -#define SMBHSTADDR 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBHSTBLKDAT 0x7 - -#define SMBSLVCTRL 0x8 -#define SMBSLVCMD_SHADOW 0x9 -#define SMBSLVEVT 0xa -#define SMBSLVDAT 0xc - -#define AB_INDX 0xcd8 -#define AB_DATA (AB_INDX + 4) - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - -#define abcfg_reg(reg, mask, val) \ - alink_ab_indx((ABCFG), (reg), (mask), (val)) -#define axcfg_reg(reg, mask, val) \ - alink_ab_indx((AXCFG), (reg), (mask), (val)) -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXC), (reg), (mask), (val)) -#define axindxp_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXP), (reg), (mask), (val)) -#define rcindxc_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) -#define rcindxp_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) - -int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -int do_smbus_recv_byte(u32 smbus_io_base, u32 device); -int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); - -#endif diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c deleted file mode 100644 index 35c1cccdb4..0000000000 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.c +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/pci_def.h> -#include <device/device.h> -#include <stddef.h> -#include <OEM.h> /* SMBUS0_BASE_ADDRESS */ - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include <vendorcode/amd/include/Porting.h> -#include <AGESA.h> -#include "chip.h" -#include "smbus_spd.h" - -#include <northbridge/amd/agesa/dimmSpd.h> - -/* uncomment for source level debug - GDB gets really confused otherwise. */ -//#pragma optimize ("", off) - -/** - * Read a single SPD byte. If the first byte is being read, set up the - * address and offset. Following bytes auto increment. - */ -static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer, - int offset, int initial_offset) -{ - unsigned int status = -1; - UINT64 time_limit; - - /* clear status register */ - __outbyte(iobase + SMBUS_STATUS_REG, 0x1E); - - if (offset == initial_offset) { - /* Clear slave status, set offset, set slave address and start reading */ - __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x3E); - __outbyte(iobase + SMBUS_CONTROL_REG, offset); - __outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT); - __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND); - } else { - /* Issue read command - auto increments to next byte */ - __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND); - } - /* time limit to avoid hanging for unexpected error status */ - time_limit = __rdtsc() + MAX_READ_TSC_COUNT; - while (__rdtsc() <= time_limit) { - status = __inbyte(iobase + SMBUS_STATUS_REG); - if ((status & SMBUS_INTERRUPT_MASK) == 0) - continue; /* SMBusInterrupt not set, keep waiting */ - if ((status & HOSTBUSY_MASK) != 0) - continue; /* HostBusy set, keep waiting */ - break; - } - - if (status != STATUS__COMPLETED_SUCCESSFULLY) - return AGESA_ERROR; - - buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG); - return AGESA_SUCCESS; -} - -static void writePmReg(UINT8 reg, UINT8 data) -{ - __outbyte(PMIO_INDEX_REG, reg); - __outbyte(PMIO_DATA_REG, data); -} - -static void setupFch(UINT16 ioBase) -{ - /* set up SMBUS - Set to SMBUS 0 & set base address */ - /* For SB800 & Hudson1 to SB900 & Hudson 2/3 */ - writePmReg(SMBUS_BAR_HIGH_BYTE, ioBase >> 8); - writePmReg(SMBUS_BAR_LOW_BYTE, (ioBase & 0xe0) | 1); - - /* set SMBus clock to 400 KHz */ - __outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000); -} - -/** - * Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ -static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, - UINT16 count) -{ - UINT16 index; - UINT8 status; - UINT8 initial_offset = 0; - - setupFch(iobase); - - for (index = initial_offset; index < count; index++) { - status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index, - initial_offset); - if (status != AGESA_SUCCESS) - return status; - } - - return status; -} - -int smbus_readSpd(int spdAddress, char *buf, size_t len) -{ - int ioBase = SMBUS0_BASE_ADDRESS; - setupFch(ioBase); - return readspd(ioBase, spdAddress, buf, len); -} diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.h b/src/southbridge/amd/cimx/sb800/smbus_spd.h deleted file mode 100644 index e3fbd092e6..0000000000 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _SMBUS_SPD_H_ -#define _SMBUS_SPD_H_ - -#define READ_BIT 0x01 - -#define SMBUS_INTERRUPT_MASK 0x02 -#define HOSTBUSY_MASK 0x01 - -#define SMBUS_READ_BYTE_COMMAND 0x48 -#define SMBUS_READ_COMMAND 0x44 - -#define MAX_READ_TSC_COUNT (2000000000 / 10) - -#define PMIO_INDEX_REG 0xCD6 -#define PMIO_DATA_REG 0xCD7 - -#define SMBUS_BAR_LOW_BYTE 0x2C -#define SMBUS_BAR_HIGH_BYTE 0x2D - -#define SMBUS_STATUS_REG 0x00 -#define SMBUS_SLAVE_STATUS_REG 0x01 -#define SMBUS_COMMAND_REG 0x02 -#define SMBUS_CONTROL_REG 0x03 -#define SMBUS_HOST_CMD_REG 0x04 -#define SMBUS_DATA0_REG 0x05 -#define SMBUS_CLOCK_REG 0x0E - -#define STATUS__COMPLETED_SUCCESSFULLY 0x02 - -#define SMBUS_FREQUENCY_CONST 66000000 / 4 - -#endif diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c deleted file mode 100644 index 792a4a1d7e..0000000000 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <console/console.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ops.h> -#include <types.h> - -#include "SBPLATFORM.h" -#include <vendorcode/amd/cimx/sb800/ECfan.h> - -#define AMD_SB_SPI_TX_LEN 8 - -static uintptr_t spibar; - -static void reset_internal_fifo_pointer(void) -{ - do { - write8((void *)(spibar + 2), - read8((void *)(spibar + 2)) | 0x10); - } while (read8((void *)(spibar + 0xD)) & 0x7); -} - -static void execute_command(void) -{ - write8((void *)(spibar + 2), read8((void *)(spibar + 2)) | 1); - - while ((read8((void *)(spibar + 2)) & 1) && - (read8((void *)(spibar + 3)) & 0x80)); -} - -void spi_init(void) -{ - struct device *dev; - - dev = pcidev_on_root(0x14, 3); - spibar = pci_read_config32(dev, 0xA0) & ~0x1F; -} - -static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - /* First byte is cmd which can not be sent through FIFO. */ - u8 cmd = *(u8 *)dout++; - u8 readoffby1; - u8 readwrite; - size_t count; - - bytesout--; - - /* - * Check if this is a write command attempting to transfer more bytes - * than the controller can handle. Iterations for writes are not - * supported here because each SPI write command needs to be preceded - * and followed by other SPI commands, and this sequence is controlled - * by the SPI chip driver. - */ - if (bytesout > AMD_SB_SPI_TX_LEN) { - printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); - return -1; - } - - readoffby1 = bytesout ? 0 : 1; - - readwrite = (bytesin + readoffby1) << 4 | bytesout; - write8((void *)(spibar + 1), readwrite); - write8((void *)(spibar + 0), cmd); - - reset_internal_fifo_pointer(); - for (count = 0; count < bytesout; count++, dout++) { - write8((void *)(spibar + 0x0C), *(u8 *)dout); - } - - reset_internal_fifo_pointer(); - execute_command(); - - reset_internal_fifo_pointer(); - /* Skip the bytes we sent. */ - for (count = 0; count < bytesout; count++) { - read8((void *)(spibar + 0x0C)); - } - - reset_internal_fifo_pointer(); - for (count = 0; count < bytesin; count++, din++) { - *(u8 *)din = read8((void *)(spibar + 0x0C)); - } - - return 0; -} - -static void ImcSleep(void) -{ - u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ - u8 reg0_val = 0; /* clear response register */ - u8 reg1_val = 0xB4; /* request ownership flag */ - - WriteECmsg(MSG_REG0, AccWidthUint8, ®0_val); - WriteECmsg(MSG_REG1, AccWidthUint8, ®1_val); - WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); - - WaitForEcLDN9MailboxCmdAck(); -} - -static void ImcWakeup(void) -{ - u8 cmd_val = 0x96; /* Kick off IMC Mailbox command 96 */ - u8 reg0_val = 0; /* clear response register */ - u8 reg1_val = 0xB5; /* release ownership flag */ - - WriteECmsg(MSG_REG0, AccWidthUint8, ®0_val); - WriteECmsg(MSG_REG1, AccWidthUint8, ®1_val); - WriteECmsg(MSG_SYS_TO_IMC, AccWidthUint8, &cmd_val); - - WaitForEcLDN9MailboxCmdAck(); -} - -int chipset_volatile_group_begin(const struct spi_flash *flash) -{ - if (!CONFIG(SB800_IMC_FWM)) - return 0; - - ImcSleep(); - return 0; -} - -int chipset_volatile_group_end(const struct spi_flash *flash) -{ - if (!CONFIG(SB800_IMC_FWM)) - return 0; - - ImcWakeup(); - return 0; -} - -static int xfer_vectors(const struct spi_slave *slave, - struct spi_op vectors[], size_t count) -{ - return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer); -} - -static const struct spi_ctrlr spi_ctrlr = { - .xfer_vector = xfer_vectors, - .max_xfer_size = AMD_SB_SPI_TX_LEN, - .flags = SPI_CNTRLR_DEDUCT_CMD_LEN, -}; - -const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { - { - .ctrlr = &spi_ctrlr, - .bus_start = 0, - .bus_end = 0, - }, -}; - -const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index ca6c75647c..e086dc3a20 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -1,5 +1 @@ -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += amd_pci_util.c diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 9a2c7445db..10f25a1ef8 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -144,9 +144,4 @@ Method(_INI, 0) { /* DBGO(\_REV) */ /* DBGO("\n") */ -#if CONFIG(HUDSON_IMC_FWM) -#if CONFIG(ACPI_ENABLE_THERMAL_ZONE) - ITZE() /* enable IMC Fan Control*/ -#endif -#endif } /* End Method(_SB._INI) */ diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index e9b26e0ad0..1e9864a2ee 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -88,8 +88,7 @@ static void hudson_final(void *chip_info) { if (CONFIG(HUDSON_IMC_FWM)) { agesawrapper_fchecfancontrolservice(); - if (!CONFIG(ACPI_ENABLE_THERMAL_ZONE)) - enable_imc_thermal_zone(); + enable_imc_thermal_zone(); } } diff --git a/src/vendorcode/amd/Makefile.inc b/src/vendorcode/amd/Makefile.inc index 9cdbe60a32..ddeb2a4959 100644 --- a/src/vendorcode/amd/Makefile.inc +++ b/src/vendorcode/amd/Makefile.inc @@ -1,2 +1 @@ subdirs-y += pi -subdirs-y += cimx diff --git a/src/vendorcode/amd/cimx/Makefile.inc b/src/vendorcode/amd/cimx/Makefile.inc deleted file mode 100644 index 33fc2e3e8f..0000000000 --- a/src/vendorcode/amd/cimx/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800 diff --git a/src/vendorcode/amd/cimx/sb800/ACPILIB.c b/src/vendorcode/amd/cimx/sb800/ACPILIB.c deleted file mode 100644 index e112fe814c..0000000000 --- a/src/vendorcode/amd/cimx/sb800/ACPILIB.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -// -// -// Routine Description: -// -// Locate ACPI table -// -// Arguments: -// -// Signature - table signature -// -//Returns: -// -// pointer to ACPI table -// -// -VOID* -ACPI_LocateTable ( - IN UINT32 Signature - ) -{ - UINT32 i; - UINT32* RsdPtr; - UINT32* Rsdt; - UINTN tableOffset; - DESCRIPTION_HEADER* CurrentTable; - - RsdPtr = (UINT32*) (UINTN)0xe0000; - Rsdt = NULL; - do { - if ( *RsdPtr == Int32FromChar('R', 'S', 'D', ' ') && *(RsdPtr + 1) == Int32FromChar('P', 'T', 'R', ' ')) { - Rsdt = (UINT32*) (UINTN) ((RSDP_HEADER*)RsdPtr)->RsdtAddress; - break; - } - RsdPtr += 4; - } while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 ); - if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) { - for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) { - tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4); - CurrentTable = (DESCRIPTION_HEADER*)tableOffset; - if ( CurrentTable->Signature == Signature ) { - return CurrentTable; - } - } - } - return NULL; -} - -// -// -// Routine Description: -// -// Update table checksum -// -// Arguments: -// -// TablePtr - table pointer -// -// Returns: -// -// none -// -// -VOID -ACPI_SetTableChecksum ( - IN VOID* TablePtr - ) -{ - UINT8 Checksum; - Checksum = 0; - ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0; - Checksum = ACPI_GetTableChecksum (TablePtr); - ((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8)(0x100 - Checksum); -} - -// -// -// Routine Description: -// -// Get table checksum -// -// Arguments: -// -// TablePtr - table pointer -// -// Returns: -// -// none -// -// -UINT8 -ACPI_GetTableChecksum ( - IN VOID* TablePtr - ) -{ - return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length); -} - - -UINT8 -GetByteSum ( - IN VOID* pData, - IN UINT32 Length - ) -{ - UINT32 i; - UINT8 Checksum; - Checksum = 0; - for ( i = 0; i < Length; i++ ) { - Checksum = Checksum + (*((UINT8*)pData + i)); - } - return Checksum; -} -VOID -GetSbAcpiMmioBase ( - OUT UINT32* AcpiMmioBase - ) -{ - UINT32 Value16; - - ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16); - *AcpiMmioBase = Value16 << 16; -} - -VOID -GetSbAcpiPmBase ( - OUT UINT16* AcpiPmBase - ) -{ - ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase); -} - diff --git a/src/vendorcode/amd/cimx/sb800/ACPILIB.h b/src/vendorcode/amd/cimx/sb800/ACPILIB.h deleted file mode 100644 index 442043a4fb..0000000000 --- a/src/vendorcode/amd/cimx/sb800/ACPILIB.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/** - * RSDP - ACPI 2.0 table RSDP - */ -typedef struct _RSDP -{ - unsigned long long Signature; /* RSDP signature "RSD PTR" */ - unsigned char Checksum; /* checksum of the first 20 bytes */ - unsigned char OEMID[6]; /* OEM ID, "LXBIOS" */ - unsigned char Revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */ - unsigned int RsdtAddress; /* physical address of RSDT */ - unsigned int Length; /* total length of RSDP (including extended part) */ - unsigned long long XsdtAddress; /* physical address of XSDT */ - unsigned char ExtendedChecksum; /* chechsum of whole table */ - unsigned char Reserved[3]; -} RSDP_HEADER; - - -/** - * DESCRIPTION_HEADER - ACPI common table header - */ -typedef struct _DESCRIPTION_HEADER -{ - unsigned int Signature; /* ACPI signature (4 ASCII characters) */ - unsigned int Length; /* Length of table, in bytes, including header */ - unsigned char Revision; /* ACPI Specification minor version # */ - unsigned char Checksum; /* To make sum of entire table == 0 */ - unsigned char OEMID[6]; /* OEM identification */ - unsigned char OEMTableID[8]; /* OEM table identification */ - unsigned int OEMRevision; /* OEM revision number */ - unsigned int CreatorID; /* ASL compiler vendor ID */ - unsigned int CreatorRevision; /* ASL compiler revision number */ -} DESCRIPTION_HEADER; - -void* ACPI_LocateTable (IN unsigned int Signature); -void ACPI_SetTableChecksum (IN void* TablePtr); -unsigned char ACPI_GetTableChecksum (IN void* TablePtr); -unsigned char GetByteSum (IN void* pData, IN unsigned int Length); diff --git a/src/vendorcode/amd/cimx/sb800/AMDLIB.c b/src/vendorcode/amd/cimx/sb800/AMDLIB.c deleted file mode 100644 index 90e9e2792e..0000000000 --- a/src/vendorcode/amd/cimx/sb800/AMDLIB.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -UINT8 -getNumberOfCpuCores ( - OUT VOID - ) -{ - UINT8 Result; - Result = 1; - Result = ReadNumberOfCpuCores (); - return Result; -} - -UINT32 -readAlink ( - IN UINT32 Index - ) -{ - UINT32 Data; - WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index); - ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data); - //Clear Index - Index = 0; - WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index); - return Data; -} - -VOID -writeAlink ( - IN UINT32 Index, - IN UINT32 Data - ) -{ - WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index); - WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data); - //Clear Index - Index = 0; - WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index); -} - -VOID -rwAlink ( - IN UINT32 Index, - IN UINT32 AndMask, - IN UINT32 OrMask - ) -{ - UINT32 AccesType; - AccesType = Index & 0xE0000000; - if (AccesType == (AXINDC << 29)) { - writeAlink ((SB_AX_INDXC_REG30 | AccesType), Index & 0x1FFFFFFF); - Index = (SB_AX_DATAC_REG34 | AccesType); - } else if (AccesType == (AXINDP << 29)) { - writeAlink ((SB_AX_INDXP_REG38 | AccesType), Index & 0x1FFFFFFF); - Index = (SB_AX_DATAP_REG3C | AccesType); - } - writeAlink (Index, (readAlink (Index) & AndMask) | OrMask ); -} - diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c deleted file mode 100644 index 26d9110dff..0000000000 --- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c +++ /dev/null @@ -1,150 +0,0 @@ -/** - * @file - * - * Southbridge IO access common routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -/*----------------------------------------------------------------------------------------*/ -/** - * SbStall - Delay routine - * - * - * - * @param[in] uSec - * - */ -VOID -SbStall ( - IN UINT32 uSec - ) -{ - UINT16 timerAddr; - UINT32 startTime; - UINT32 elapsedTime; - - ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr); - if ( timerAddr == 0 ) { - uSec = uSec / 2; - while ( uSec != 0 ) { - ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime)); - uSec--; - } - } else { - ReadIO (timerAddr, AccWidthUint32, &startTime); - for ( ;; ) { - ReadIO (timerAddr, AccWidthUint32, &elapsedTime); - if ( elapsedTime < startTime ) { - elapsedTime = elapsedTime + 0xFFFFFFFF - startTime; - } else { - elapsedTime = elapsedTime - startTime; - } - if ( (elapsedTime * 28 / 100) > uSec ) { - break; - } - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * SbReset - Generate a reset command - * - * - * - * @param[in] OpFlag - Dummy - * - */ -VOID -SbReset ( - IN UINT8 OpFlag - ) -{ - RWIO (0xcf9, AccWidthUint8, 0x0, 0x06); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * outPort80 - Send data to PORT 80 (debug port) - * - * - * - * @param[in] pcode - debug code (32 bits) - * - */ -VOID -outPort80 ( - IN UINT32 pcode - ) -{ - WriteIO (0x80, AccWidthUint8, &pcode); - return; -} - -/** - * AmdSbCopyMem - Memory copy - * - * @param[in] pDest - Destance address point - * @param[in] pSource - Source Address point - * @param[in] Length - Data length - * - */ -VOID -AmdSbCopyMem ( - IN VOID* pDest, - IN VOID* pSource, - IN UINTN Length - ) -{ - UINTN i; - UINT8 *Ptr; - UINT8 *Source; - Ptr = (UINT8*)pDest; - Source = (UINT8*)pSource; - for (i = 0; i < Length; i++) { - *Ptr = *Source; - Source++; - Ptr++; - } -} diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h deleted file mode 100644 index 3b09dac71c..0000000000 --- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h +++ /dev/null @@ -1,124 +0,0 @@ -/** - * @file - * - * Southbridge IO access common routine define file - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ -#define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ - -#include "cbtypes.h" - -//AMDSBLIB Routines - -/** - * SbStall - Delay routine - * - * - * - * @param[in] uSec - * - */ -void SbStall (IN unsigned int uSec); - -/** - * SbReset - Generate a reset command - * - * - * - * @param[in] OpFlag - Dummy - * - */ -void SbReset (IN unsigned char OpFlag); - -/** - * outPort80 - Send data to PORT 80 (debug port) - * - * - * - * @param[in] pcode - debug code (32 bits) - * - */ -void outPort80 (IN unsigned int pcode); - -/** - * getEfuseStatue - Get Efuse status - * - * - * @param[in] Value - Return Chip strap status - * - */ -void getEfuseStatus (IN void* Value); - -/** - * AmdSbDispatcher - Dispatch Southbridge function - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -AGESA_STATUS AmdSbDispatcher (IN void *pConfig); - -/** - * AmdSbCopyMem - Memory copy - * - * @param[in] pDest - Destance address point - * @param[in] pSource - Source Address point - * @param[in] Length - Data length - * - */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); - - -/* SB800 CIMx and AGESA V5 can share lib functions */ -unsigned char ReadIo8(IN unsigned short Address); -unsigned short ReadIo16(IN unsigned short Address); -unsigned int ReadIo32(IN unsigned short Address); -void WriteIo8(IN unsigned short Address, IN unsigned char Data); -void WriteIo16(IN unsigned short Address, IN unsigned short Data); -void WriteIo32(IN unsigned short Address, IN unsigned int Data); -//void CpuidRead(IN unsigned int CpuidFcnAddress, OUT CPUID_DATA *Value); -void CpuidRead(unsigned int CpuidFcnAddress, CPUID_DATA *Value); -unsigned char ReadNumberOfCpuCores(void); - -#endif diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c deleted file mode 100644 index d9e1f13c4a..0000000000 --- a/src/vendorcode/amd/cimx/sb800/AZALIA.c +++ /dev/null @@ -1,509 +0,0 @@ -/** - * @file - * - * Config Southbridge HD Audio Controller - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ - -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -// -// Declaration of local functions -// - -VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum); -VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0); - -/** - * Pin Config for ALC880, ALC882 and ALC883. - * - * - * - */ -static const CODECENTRY AzaliaCodecAlc882Table[] = -{ - {0x14, 0x01014010}, - {0x15, 0x01011012}, - {0x16, 0x01016011}, - {0x17, 0x01012014}, - {0x18, 0x01A19030}, - {0x19, 0x411111F0}, - {0x1a, 0x01813080}, - {0x1b, 0x411111F0}, - {0x1C, 0x411111F0}, - {0x1d, 0x411111F0}, - {0x1e, 0x01441150}, - {0x1f, 0x01C46160}, - {0xff, 0xffffffff} -}; - -/** - * Pin Config for ALC0262. - * - * - * - */ -static const CODECENTRY AzaliaCodecAlc262Table[] = -{ - {0x14, 0x01014010}, - {0x15, 0x411111F0}, - {0x16, 0x411111F0}, - {0x18, 0x01A19830}, - {0x19, 0x02A19C40}, - {0x1a, 0x01813031}, - {0x1b, 0x02014C20}, - {0x1c, 0x411111F0}, - {0x1d, 0x411111F0}, - {0x1e, 0x0144111E}, - {0x1f, 0x01C46150}, - {0xff, 0xffffffff} -}; - -/** - * Pin Config for ALC0269. - * - * - * - */ -static const CODECENTRY AzaliaCodecAlc269Table[] = -{ - {0x12, 0x99A30960}, - {0x14, 0x99130110}, - {0x15, 0x0221401F}, - {0x16, 0x99130120}, - {0x18, 0x01A19850}, - {0x19, 0x02A15951}, - {0x1a, 0x01813052}, - {0x1b, 0x0181405F}, - {0x1d, 0x40134601}, - {0x1e, 0x01441130}, - {0x11, 0x18567140}, - {0x20, 0x0030FFFF}, - {0xff, 0xffffffff} -}; - -/** - * Pin Config for ALC0861. - * - * - * - */ -static const CODECENTRY AzaliaCodecAlc861Table[] = -{ - {0x01, 0x8086C601}, - {0x0B, 0x01014110}, - {0x0C, 0x01813140}, - {0x0D, 0x01A19941}, - {0x0E, 0x411111F0}, - {0x0F, 0x02214420}, - {0x10, 0x02A1994E}, - {0x11, 0x99330142}, - {0x12, 0x01451130}, - {0x1F, 0x411111F0}, - {0x20, 0x411111F0}, - {0x23, 0x411111F0}, - {0xff, 0xffffffff} -}; - -/** - * Pin Config for ALC0889. - * - * - * - */ -static const CODECENTRY AzaliaCodecAlc889Table[] = -{ - {0x11, 0x411111F0}, - {0x14, 0x01014010}, - {0x15, 0x01011012}, - {0x16, 0x01016011}, - {0x17, 0x01013014}, - {0x18, 0x01A19030}, - {0x19, 0x411111F0}, - {0x1a, 0x411111F0}, - {0x1b, 0x411111F0}, - {0x1C, 0x411111F0}, - {0x1d, 0x411111F0}, - {0x1e, 0x01442150}, - {0x1f, 0x01C42160}, - {0xff, 0xffffffff} -}; - -/** - * Pin Config for ADI1984. - * - * - * - */ -static const CODECENTRY AzaliaCodecAd1984Table[] = -{ - {0x11, 0x0221401F}, - {0x12, 0x90170110}, - {0x13, 0x511301F0}, - {0x14, 0x02A15020}, - {0x15, 0x50A301F0}, - {0x16, 0x593301F0}, - {0x17, 0x55A601F0}, - {0x18, 0x55A601F0}, - {0x1A, 0x91F311F0}, - {0x1B, 0x014511A0}, - {0x1C, 0x599301F0}, - {0xff, 0xffffffff} -}; - -/** - * FrontPanel Config table list - * - * - * - */ -static const CODECENTRY FrontPanelAzaliaCodecTableList[] = -{ - {0x19, 0x02A19040}, - {0x1b, 0x02214020}, - {0xff, 0xffffffff} -}; - -/** - * Current HD Audio support codec list - * - * - * - */ -static const CODECTBLLIST azaliaCodecTableList[] = -{ - {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, - {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, - {0x010ec0883, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, - {0x010ec0885, (CODECENTRY*)&AzaliaCodecAlc882Table[0]}, - {0x010ec0889, (CODECENTRY*)&AzaliaCodecAlc889Table[0]}, - {0x010ec0262, (CODECENTRY*)&AzaliaCodecAlc262Table[0]}, - {0x010ec0269, (CODECENTRY*)&AzaliaCodecAlc269Table[0]}, - {0x010ec0861, (CODECENTRY*)&AzaliaCodecAlc861Table[0]}, - {0x011d41984, (CODECENTRY*)&AzaliaCodecAd1984Table[0]}, - { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF} -}; - -/** - * azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -azaliaInitBeforePciEnum ( - IN AMDSBCFG* pConfig - ) -{ - if ( pConfig->AzaliaController == 1 ) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); - } else { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0); - if ( pConfig->BuildParameters.HdAudioMsi) { - RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8); - RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16); - } - } -} - -/** - * azaliaInitAfterPciEnum - Config HD Audio after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -azaliaInitAfterPciEnum ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 Data; - UINT8 i; - UINT8 dbEnableAzalia; - UINT8 dbPinRouting; - UINT8 dbChannelNum; - UINT8 dbTempVariable; - UINT16 dwTempVariable; - UINT32 ddBAR0; - dbEnableAzalia = 0; - dbChannelNum = 0; - dbTempVariable = 0; - dwTempVariable = 0; - ddBAR0 = 0; - - if ( pConfig->AzaliaController == 1 ) { - return; - } - - if ( pConfig->AzaliaController != 1 ) { - RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1); - if ( pConfig->BuildParameters.AzaliaSsid != 0 ) { - RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid); - } - ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0); - if ( ddBAR0 != 0 ) { - if ( ddBAR0 != 0xFFFFFFFF ) { - ddBAR0 &= ~(0x03FFF); - dbEnableAzalia = 1; - } - } - } - - if ( dbEnableAzalia ) { - // Get SDIN Configuration - if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) { - RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00); - } else { - RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01); - } - if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) { - RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00); - } else { - RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01); - } - if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) { - RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00); - } else { - RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01); - } - if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) { - RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00); - } else { - RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01); - } - // INT#A Azalia resource - Data = 0x93; // Azalia APIC index - WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data); - Data = 0x10; // IRQ16 (INTA#) - WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data); - - i = 11; - do { - ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - dbTempVariable |= BIT0; - WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - SbStall (1000); - ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - i--; - } while ((! (dbTempVariable & BIT0)) && (i > 0) ); - - if ( i == 0 ) { - return; - } - - SbStall (1000); - ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable); - if ( dwTempVariable & 0x0F ) { - - //atleast one azalia codec found - // ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux - //ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting); - dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin; - do { - if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) { -// dbChannelNum = 3; - configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum); - } - dbPinRouting >>= 2; - dbChannelNum++; - } while ( dbChannelNum != 4 ); - } else { - //No Azalia codec found - if ( pConfig->AzaliaController != 2 ) { - dbEnableAzalia = 0; //set flag to disable Azalia - } - } - } - - if ( dbEnableAzalia ) { - //redo clear reset - do { - dwTempVariable = 0; - WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable); - ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - dbTempVariable &= ~(BIT0); - WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable); - } while ( dbTempVariable & BIT0 ); - - if ( pConfig->AzaliaSnoop == 1 ) { - RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0); - } - } else { - //disable Azalia controller - RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0); - // RWPMIO (SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~BIT3, 0); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); - // RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0); - } -} - -/** - * configureAzaliaPinCmd - Configuration HD Audio PIN Command - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * @param[in] ddBAR0 HD Audio BAR0 base address. - * @param[in] dbChannelNum Channel Number. - * - */ -VOID -configureAzaliaPinCmd ( - IN AMDSBCFG* pConfig, - IN UINT32 ddBAR0, - IN UINT8 dbChannelNum - ) -{ - UINT32 ddTempVariable; - UINT32 ddChannelNum; - CODECTBLLIST* ptempAzaliaOemCodecTablePtr; - CODECENTRY* tempAzaliaCodecEntryPtr; - - if ( (pConfig->AzaliaPinCfg) != 1 ) { - return; - } - - ddChannelNum = dbChannelNum << 28; - ddTempVariable = 0xF0000; - ddTempVariable |= ddChannelNum; - - WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable); - SbStall (600); - ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable); - - if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) { - ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]); - } else { - ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr; - } - - while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) { - if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) { - break; - } else { - ++ptempAzaliaOemCodecTablePtr; - } - } - - if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) { - tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr; - - if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) { - tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr); - } - configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); - if ( pConfig->AzaliaFrontPanel != 1 ) { - if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) { - if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) { - tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]); - } else { - tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr; - } - configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0); - } - } - } -} - -/** - * configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table - * - * - * @param[in] tempAzaliaCodecEntryPtr HD Audio Codec table structure pointer. - * @param[in] ddChannelNum HD Audio Channel Number. - * @param[in] ddBAR0 HD Audio BAR0 base address. - * - */ -VOID -configureAzaliaSetConfigD4Dword ( - IN CODECENTRY* tempAzaliaCodecEntryPtr, - IN UINT32 ddChannelNum, - IN UINT32 ddBAR0 - ) -{ - UINT8 dbtemp1; - UINT8 dbtemp2; - UINT8 i; - UINT32 ddtemp; - UINT32 ddtemp2; - ddtemp = 0; - ddtemp2 = 0; - while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) { - dbtemp1 = 0x20; - if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) { - dbtemp1 = 0x24; - } - - ddtemp = tempAzaliaCodecEntryPtr->Nid; - ddtemp &= 0xff; - ddtemp <<= 20; - ddtemp |= ddChannelNum; - - ddtemp |= (0x700 << 8); - for ( i = 4; i > 0; i-- ) { - do { - ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2); - } while ( ddtemp2 & BIT0 ); - - dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff); - ddtemp = (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2; - WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp); - SbStall (60); - } - ++tempAzaliaCodecEntryPtr; - } -} diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c deleted file mode 100644 index faec104232..0000000000 --- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - * @file - * - * Function dispatcher. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ - -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- -*/ - - -// -// Declaration of local functions -// - -VOID saveConfigPointer (IN AMDSBCFG* pConfig); - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/** - * AmdSbDispatcher - Dispatch Southbridge function - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -AGESA_STATUS -AmdSbDispatcher ( - IN VOID *pConfig - ) -{ - AGESA_STATUS Status; - - Status = AGESA_UNSUPPORTED; - - saveConfigPointer (pConfig); - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) { - sbPowerOnInit ((AMDSBCFG*) pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) { - sbBeforePciInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) { - sbAfterPciInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) { - sbMidPostInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) { - sbLatePost ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) { - sbBeforePciRestoreInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) { - sbAfterPciRestoreInit ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) { - sbSmmService ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) { - sbSmmAcpiOn ((AMDSBCFG*)pConfig); - } - - if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) { - sbECfancontrolservice((AMDSBCFG*)pConfig); - } - return Status; -} - -/** - * saveConfigPointer - Verify Southbridge CIMx module - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -saveConfigPointer ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 dbReg; - UINT8 i; - UINT32 ddValue; - - ddValue = (UINT32) (UINTN)pConfig; // Needs to live below 4G - dbReg = SB_ECMOS_REG08; - - for ( i = 0; i <= 3; i++ ) { - WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg); - WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue); - ddValue = (ddValue >> 8); - dbReg++; - } -} diff --git a/src/vendorcode/amd/cimx/sb800/EC.c b/src/vendorcode/amd/cimx/sb800/EC.c deleted file mode 100644 index c407537301..0000000000 --- a/src/vendorcode/amd/cimx/sb800/EC.c +++ /dev/null @@ -1,131 +0,0 @@ - -/** - * @file - * - * Config Southbridge EC Controller - * - * Init EC features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -#ifndef NO_EC_SUPPORT - -/** - * Config EC controller during power-on - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -ecPowerOnInit ( - IN AMDSBCFG* pConfig - ) -{ - //Enable config mode - EnterEcConfig (); - - //Do settings for mailbox - logical device 0x09 - RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox) - RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port - RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port - RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 - - if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) { - //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3); - - //Disable LPC Decoding of port 60/64 - RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0); - - //Enable logical device 0x07 (Keyboard controller) - RWEC8 (0x07, 0x00, 0x07); - RWEC8 (0x30, 0x00, 0x01); - } - - if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) { - //Logical device 0x03 - RWEC8 (0x07, 0x00, 0x03); - RWEC8 (0x60, 0x00, 0x00); - RWEC8 (0x61, 0x00, 0x62); - RWEC8 (0x30, 0x00, 0x01); //;Enable Device 8 - } - - //Enable EC (IMC) to generate SMI to BIOS - RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6); - ExitEcConfig (); -} - -/** - * Config EC controller before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -ecInitBeforePciEnum ( - IN AMDSBCFG* pConfig - ) -{ - /* AMDSBCFG* pTmp; // dummy code */ - /* pTmp = pConfig; */ -} - -/** - * Prepare EC controller to boot to OS. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -ecInitLatePost ( - IN AMDSBCFG* pConfig - ) -{ - /* AMDSBCFG* pTmp; // dummy code */ - /* pTmp = pConfig; */ -} -#endif diff --git a/src/vendorcode/amd/cimx/sb800/ECLIB.c b/src/vendorcode/amd/cimx/sb800/ECLIB.c deleted file mode 100644 index 54d87e7930..0000000000 --- a/src/vendorcode/amd/cimx/sb800/ECLIB.c +++ /dev/null @@ -1,156 +0,0 @@ -/** - * @file - * - * Southbridge EC IO access common routine - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -// #ifndef NO_EC_SUPPORT - -/*----------------------------------------------------------------------------------------*/ -/** - * EnterEcConfig - Force EC into Config mode - * - * - * - * - */ -VOID -EnterEcConfig ( - ) -{ - UINT16 dwEcIndexPort; - - ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); - dwEcIndexPort &= ~(BIT0); - RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * ExitEcConfig - Force EC exit Config mode - * - * - * - * - */ -VOID -ExitEcConfig ( - ) -{ - UINT16 dwEcIndexPort; - - ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); - dwEcIndexPort &= ~(BIT0); - RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * ReadEC8 - Read EC register data - * - * - * - * @param[in] Address - EC Register Offset Value - * @param[in] Value - Read Data Buffer - * - */ -VOID -ReadEC8 ( - IN UINT8 Address, - IN UINT8* Value - ) -{ - UINT16 dwEcIndexPort; - - ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); - dwEcIndexPort &= ~(BIT0); - WriteIO (dwEcIndexPort, AccWidthUint8, &Address); - ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * WriteEC8 - Write date into EC register - * - * - * - * @param[in] Address - EC Register Offset Value - * @param[in] Value - Write Data Buffer - * - */ -VOID -WriteEC8 ( - IN UINT8 Address, - IN UINT8* Value - ) -{ - UINT16 dwEcIndexPort; - - ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort); - dwEcIndexPort &= ~(BIT0); - - WriteIO (dwEcIndexPort, AccWidthUint8, &Address); - WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * RWEC8 - Read/Write EC register - * - * - * - * @param[in] Address - EC Register Offset Value - * @param[in] AndMask - Data And Mask 8 bits - * @param[in] OrMask - Data OR Mask 8 bits - * - */ -VOID -RWEC8 ( - IN UINT8 Address, - IN UINT8 AndMask, - IN UINT8 OrMask - ) -{ - UINT8 Result; - ReadEC8 (Address, &Result); - Result = (Result & AndMask) | OrMask; - WriteEC8 (Address, &Result); -} - -// #endif - diff --git a/src/vendorcode/amd/cimx/sb800/ECfan.h b/src/vendorcode/amd/cimx/sb800/ECfan.h deleted file mode 100644 index 3fd5fea9dc..0000000000 --- a/src/vendorcode/amd/cimx/sb800/ECfan.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "cbtypes.h" - -VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value); -VOID WaitForEcLDN9MailboxCmdAck (VOID); -VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value); - -// IMC Message Register Software Interface -#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3) - -#define MSG_SYS_TO_IMC 0x80 -#define Fun_80 0x80 -#define Fun_81 0x81 -#define Fun_82 0x82 -#define Fun_83 0x83 -#define Fun_84 0x84 -#define Fun_85 0x85 -#define Fun_86 0x86 -#define Fun_87 0x87 -#define Fun_88 0x88 -#define Fun_89 0x89 -#define Fun_90 0x90 -#define MSG_IMC_TO_SYS 0x81 -#define MSG_REG0 0x82 -#define MSG_REG1 0x83 -#define MSG_REG2 0x84 -#define MSG_REG3 0x85 -#define MSG_REG4 0x86 -#define MSG_REG5 0x87 -#define MSG_REG6 0x88 -#define MSG_REG7 0x89 -#define MSG_REG8 0x8A -#define MSG_REG9 0x8B -#define MSG_REGA 0x8C -#define MSG_REGB 0x8D -#define MSG_REGC 0x8E -#define MSG_REGD 0x8F - - diff --git a/src/vendorcode/amd/cimx/sb800/ECfanLIB.c b/src/vendorcode/amd/cimx/sb800/ECfanLIB.c deleted file mode 100644 index 9ac6c880b4..0000000000 --- a/src/vendorcode/amd/cimx/sb800/ECfanLIB.c +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file - * - * Southbridge EC IO access common routine - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "ECfan.h" - -VOID -ReadECmsg ( - IN UINT8 Address, - IN UINT8 OpFlag, - OUT VOID* Value - ) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - if (OpFlag == 0x02) OpFlag = 0x03; - for (i = 0; i <= OpFlag; i++) { - WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS - Address++; - ReadIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS - } -} - - -VOID -WriteECmsg ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - UINT8 i; - - OpFlag = OpFlag & 0x7f; - if (OpFlag == 0x02) OpFlag = 0x03; - for (i = 0; i <= OpFlag; i++) { - WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS - Address++; - WriteIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS - } -} - -VOID -WaitForEcLDN9MailboxCmdAck ( - VOID - ) -{ - UINT8 Msgdata; - UINT16 Delaytime; - Msgdata = 0; - for (Delaytime = 0; Delaytime <= 500; Delaytime++) { - ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata); - if ( Msgdata == 0xfa) { - break; - } - SbStall (1000); // Wait for 1ms - } -} - - diff --git a/src/vendorcode/amd/cimx/sb800/ECfanc.c b/src/vendorcode/amd/cimx/sb800/ECfanc.c deleted file mode 100644 index 151d882557..0000000000 --- a/src/vendorcode/amd/cimx/sb800/ECfanc.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#include "SBPLATFORM.h" -#include "ECfan.h" -/** - * Table for Function Number - * - * - * - * - */ -static const UINT8 FunctionNumber[] = -{ - Fun_81, - Fun_83, - Fun_85, - Fun_89, -}; - -/** - * Table for Max Thermal Zone - * - * - * - * - */ -static const UINT8 MaxZone[] = -{ - 4, - 4, - 4, - 4, -}; - -/** - * Table for Max Register - * - * - * - * - */ -static const UINT8 MaxRegister[] = -{ - MSG_REG9, - MSG_REGB, - MSG_REG9, - MSG_REGA, -}; - -/*------------------------------------------------------------------------------- -;Procedure: IsZoneFuncEnable -; -;Description: This routine will check every zone support function with BitMap from user define -; -; -;Exit: None -; -;Modified: None -; -;----------------------------------------------------------------------------- -*/ -BOOLEAN -IsZoneFuncEnable ( - UINT16 Flag, - UINT8 func, - UINT8 Zone -) -{ - return (BOOLEAN)(((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone)); -} - -/*------------------------------------------------------------------------------- -;Procedure: sbECfancontrolservice -; -;Description: This routine service EC fan policy -; -; -;Exit: None -; -;Modified: None -; -;----------------------------------------------------------------------------- -*/ -VOID -sbECfancontrolservice ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 ZoneNum; - UINT8 FunNum; - UINT8 RegNum; - UINT8 * CurPoint; - UINT8 FunIndex; - BOOLEAN IsSendEcMsg; - - CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1); - for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) { - FunNum = FunctionNumber[FunIndex]; - for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { - IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); - for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { - if (IsSendEcMsg) { - WriteECmsg (RegNum, AccWidthUint8, CurPoint); // - } - CurPoint += 1; - } - if (IsSendEcMsg) { - WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number - WaitForEcLDN9MailboxCmdAck (); - } - } - } - CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0; - for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) { - FunNum = FunctionNumber[FunIndex]; - for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) { - IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum); - for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) { - if (IsSendEcMsg) { - WriteECmsg (RegNum, AccWidthUint8, CurPoint); // - } - CurPoint += 1; - } - if (IsSendEcMsg) { - WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number - WaitForEcLDN9MailboxCmdAck (); - } - } - } -} - -/*------------------------------------------------------------------------------- -;Procedure: SBIMCFanInitializeS3 -; -;Description: This routine initialize IMC fan when S3 resume -; -; -;Exit: None -; -;Modified: None -; -;----------------------------------------------------------------------------- -*/ -VOID -SBIMCFanInitializeS3 (VOID) -{ - UINT8 dbPortStatus,Value80,Value82,Value83,Value84; - - getChipSysMode (&dbPortStatus); - if ((dbPortStatus & ChipSysEcEnable) != 0) { - Value80 = 0x98; - Value82 = 0x00; - Value83 = 0x02; - Value84 = 0x00; - - // Clear MSG_REG0 to receive acknowledge byte - WriteECmsg (MSG_REG0, AccWidthUint8, &Value82); - - // Set MSG_REG1 - // 0x02 - Notify IMC that the system is waken from any sleep state - WriteECmsg (MSG_REG1, AccWidthUint8, &Value83); - - // Set timeout counter value to 00 which disables watchdog timer - WriteECmsg (MSG_REG2, AccWidthUint8, &Value84); - - // Write mailbox function number to kick off the command - // 0x98 - IMC System Sleep and Wake Services - WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Value80); - - // Read acknowledge byte to make sure function is executed properly - WaitForEcLDN9MailboxCmdAck (); - } -} diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c deleted file mode 100644 index ec2dd6e7c4..0000000000 --- a/src/vendorcode/amd/cimx/sb800/GEC.c +++ /dev/null @@ -1,143 +0,0 @@ -/** - * @file - * - * Config Southbridge GEC controller - * - * Init GEC features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -/** - * gecInitBeforePciEnum - Config GEC controller before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -gecInitBeforePciEnum ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 cimSBGecDebugBus; - UINT8 cimSBGecPwr; - - cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus; - cimSBGecPwr = (UINT8) pConfig->SBGecPwr; -#if SB_CIMx_PARAMETER == 0 - cimSBGecDebugBus = cimSBGecDebugBusDefault; - cimSBGecPwr = cimSBGecPwrDefault; -#endif - if ( pConfig->GecConfig == 0) { - // GEC Enabled - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01); - RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01); - //RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5)); - } else { - // GEC Disabled - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0); - return; //return if GEC controller is disabled. - } - if ( cimSBGecDebugBus == 1) { - // GEC Debug Bus Enabled - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3); - } else { - // GEC Debug Bus Disabled - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00); - } -} - -/** - * gecInitAfterPciEnum - Config GEC controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -gecInitAfterPciEnum ( - IN AMDSBCFG* pConfig - ) -{ - VOID* GecRomAddress; - VOID* GecShadowRomAddress; - UINT32 ddTemp; - UINT8 dbVar; - UINT8 dbTemp; - if ( pConfig->GecConfig == 0) { - dbVar = 0; - ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); - dbTemp = 0x07; - WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp); - if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) { - GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr; - GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase; - AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100); - ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp); - ddTemp = ddTemp & 0xFFFFFFF0; - RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29); - } - WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar); - } -} - -/** - * gecInitLatePost - Prepare GEC controller to boot to OS. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -gecInitLatePost ( - IN AMDSBCFG* pConfig - ) -{ - /* if ( !pConfig->GecConfig == 0) { */ - /* return; //return if GEC controller is disabled. */ - /* } */ -} diff --git a/src/vendorcode/amd/cimx/sb800/Gpp.c b/src/vendorcode/amd/cimx/sb800/Gpp.c deleted file mode 100644 index e7ff2eaab2..0000000000 --- a/src/vendorcode/amd/cimx/sb800/Gpp.c +++ /dev/null @@ -1,900 +0,0 @@ - -/** - * @file - * - * Config Southbridge GPP controller - * - * Init GPP features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -/** - * PCIE_CAP_ID - PCIe Cap ID - * - */ -#define PCIE_CAP_ID 0x10 - -// -// Declaration of local functions -// - -/** - * PreInitGppLink - Enable GPP link training. - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - VOID PreInitGppLink (IN AMDSBCFG* pConfig); - UINT8 CheckGppLinkStatus (IN AMDSBCFG* pConfig); - VOID AfterGppLinkInit (IN AMDSBCFG* pConfig); - VOID sbGppForceGen2 (IN UINT32 portId ); - VOID sbGppForceGen1 (IN UINT32 portId ); - VOID sbGppDisableUnusedPadMap (IN AMDSBCFG* pConfig ); - VOID sbGppSetAspm (IN UINT32 pciAddress, IN UINT8 LxState); - UINT8 sbFindPciCap (IN UINT32 pciAddress, IN UINT8 targetCapId); - -// -// Declaration of external functions -// - -// -//----------------------------------------------------------------------------------- -// Early SB800 GPP initialization sequence: -// -// 1) Set port enable bit fields by current GPP link configuration mode -// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) -// 3) Loop polling for the link status of all ports -// 4) Misc operations after link training: -// - (optional) Detect GFX device -// - Hide empty GPP configuration spaces (Disable empty GPP ports) -// - (optional) Power down unused GPP ports -// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0]) -// 5) GPP init completed -// -// -// *) Gen2 vs Gen1 -// Gen2 mode Gen1 mode -// --------------------------------------------------------------- -// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19 -// STRAP_BIF_GEN2_EN 1 0 -// -// PCIE_PHY_PLL clock locks @ 5GHz -// -// - -/** - * GPP early programming and link training. On exit all populated EPs should be fully operational. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sbPcieGppEarlyInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 TogglePort; - UINT8 portNum; - UINT32 reg32Value; - UINT8 retryCount; - UINT8 cimGppMemWrImprove; - UINT8 cimGppLaneReversal; - UINT8 cimAlinkPhyPllPowerDown; - - cimGppMemWrImprove = pConfig->GppMemWrImprove; - cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal; - cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown; -#if SB_CIMx_PARAMETER == 0 - cimGppMemWrImprove = cimGppMemWrImproveDefault; - cimGppLaneReversal = cimGppLaneReversalDefault; - cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault; -#endif - -// -// Configure NB-SB link PCIE PHY PLL power down for L1 -// - if ( cimAlinkPhyPllPowerDown == TRUE ) { - UINT32 abValue; - // Set PCIE_P_CNTL in Alink PCIEIND space - writeAlink (SB_AX_INDXC_REG30 | ((UINT32) AXINDC << 29), 0x40); - abValue = readAlink (SB_AX_DATAC_REG34 | ((UINT32) AXINDC << 29)); - abValue |= BIT12 + BIT3 + BIT0; - abValue &= ~(BIT9 + BIT4); - writeAlink (SB_AX_DATAC_REG34 | ((UINT32) AXINDC << 29), abValue); - rwAlink (SB_AX_INDXC_REG02 | ((UINT32) AXINDC << 29), ~BIT8, (BIT8)); - } - -// -// Set ABCFG 0x031C[0] = 1 enable the lane reversal support. -// - reg32Value = readAlink (SB_ABCFG_REG31C | ((UINT32) ABCFG << 29)); - if ( cimGppLaneReversal ) { - writeAlink (SB_ABCFG_REG31C | ((UINT32) ABCFG << 29), reg32Value | BIT0); - } else { - writeAlink (SB_ABCFG_REG31C | ((UINT32) ABCFG << 29), reg32Value | 0x00); - } -// -// Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function -// - reg32Value = readAlink (SB_ABCFG_REG90 | ((UINT32) ABCFG << 29)); - writeAlink (SB_ABCFG_REG90 | ((UINT32) ABCFG << 29), reg32Value | BIT20); - - -// -// Initialize and configure GPP -// - if (pConfig->GppFunctionEnable) { - // PreInit - Enable GPP link training - PreInitGppLink (pConfig); - -// -// GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1 -// GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4 -// - if ( cimGppMemWrImprove == TRUE ) { - rwAlink (SB_ABCFG_REG54 | ((UINT32) ABCFG << 29), ~BIT26, (BIT26)); - rwAlink (SB_RCINDXC_REG10 | ((UINT32) RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12)); - } - - if ( pConfig->S3Resume ) { - for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) { - reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | ((UINT32) ABCFG << 29)); - writeAlink ((SB_ABCFG_REG340 + portNum * 4) | ((UINT32) ABCFG << 29), reg32Value & ~BIT21); - } - } - // - // a) Loop polling regA5 -> LcState (timeout ~100ms); - // b) if (LcState[5:0] == 0x10), training successful, go to g); - // c) if any of (LcState[13:8], [21:16], [29:24]) == 0x29 or 0x2A: - // d) Clear De-emphasis bit for relevant ports; - // e) Toggle GPP reset signal (via OEM callback); - // f) go back to a); - // g) exit; - // - for (retryCount = 0; retryCount < MAX_GPP_RESETS; retryCount++) { - // Polling each GPP port for link status - TogglePort = CheckGppLinkStatus (pConfig); - - if (TogglePort == 0) { - break; - } else { - // Check failure port and clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) - for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) { - if (TogglePort & (1 << portNum)) { - reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | ((UINT32) ABCFG << 29)); - writeAlink ((SB_ABCFG_REG340 + portNum * 4) | ((UINT32) ABCFG << 29), reg32Value & ~BIT21); - } - sbGppForceGen1 (portNum); - } - - // Toggle GPP reset (Note this affects all SB800 GPP ports) - CallBackToOEM (CB_SBGPP_RESET_ASSERT, (UINT32)TogglePort, pConfig); - SbStall (500); - CallBackToOEM (CB_SBGPP_RESET_DEASSERT, (UINT32)TogglePort, pConfig); - } - }; - - // Misc operations after link training - AfterGppLinkInit (pConfig); - } else { - -// RPR 5.11 Power Saving With GPP Disable -// ABCFG 0xC0[8] = 0x0 -// ABCFG 0xC0[15:12] = 0xF -// Enable "Power Saving Feature for A-Link Express Lanes" -// Enable "Power Saving Feature for GPP Lanes" -// ABCFG 0x90[19] = 1 -// ABCFG 0x90[6] = 1 -// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF -// ABCFG 0xC0[7:4] = 0x0 - - rwAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), ~BIT8, (BIT4 + BIT5 + BIT6 + BIT7)); - rwAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), 0xFFFFFFFF, (BIT12 + BIT13 + BIT14 + BIT15)); - rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); - rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); - rwAlink ((SB_ABCFG_REG90 | ((UINT32) ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); - rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, 0x0fffffff); - rwAlink ((SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)), ~(BIT4 + BIT5 + BIT6 + BIT7), 0); - } - sbGppDisableUnusedPadMap ( pConfig ); -} - -/** - * PreInitGppLink - Enable GPP link training. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -PreInitGppLink ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 portMask[5] = {0x01, - 0x00, - 0x03, - 0x07, - 0x0F - }; - UINT8 cfgMode; - UINT8 portId; - UINT32 reg32Value; - UINT16 tmp16Value; - -// PCIE_GPP_ENABLE (abcfg:0xC0): -// -// GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description -// ---------------------------------------------------------------------------------- -// 0000 0-3 x4 Config -// 0001 N/A -// 0010 0-1 2-3 0 2:2 Config -// 0011 0-1 2 3 2:1:1 Config -// 0100 0 1 2 3 1:1:1:1 Config -// -// For A12 and above: -// ABCFG:0xC0[12] - Port A hold training (default 1) -// ABCFG:0xC0[13] - Port B hold training (default 1) -// ABCFG:0xC0[14] - Port C hold training (default 1) -// ABCFG:0xC0[15] - Port D hold training (default 1) -// -// - // - // Set port enable bit fields based on current GPP link configuration mode - // - cfgMode = (UINT8) pConfig->GppLinkConfig; - if ( cfgMode > GPP_CFGMODE_X1111 || cfgMode == 1 ) { - cfgMode = GPP_CFGMODE_X4000; - pConfig->GppLinkConfig = GPP_CFGMODE_X4000; - } - reg32Value = (UINT32) portMask[cfgMode]; - - // Mask out non-applicable ports according to the target link configuration mode - for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { - if (!(reg32Value & (1 << portId))) - pConfig->PORTCONFIG[portId].PortCfg.PortPresent = false; - else if (!pConfig->PORTCONFIG[portId].PortCfg.PortPresent) - reg32Value &= ~(1 << portId); - } - - // - // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0) - // - tmp16Value = (UINT16) (~reg32Value << 12); - reg32Value = (UINT32) (tmp16Value + (reg32Value << 4) + cfgMode); - writeAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), reg32Value); - - reg32Value = readAlink (0xC0 | ((UINT32) RCINDXC << 29)); - writeAlink (0xC0 | ((UINT32) RCINDXC << 29), reg32Value | 0x400); // Set STRAP_F0_MSI_EN - - // A-Link L1 Entry Delay Shortening - // AXINDP_Reg 0xA0[7:4] = 0x3 - rwAlink (SB_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30); - rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19); - rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28); - - // RPR5.22 GPP L1 Entry Delay Shortening - // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request. - // This is done to reduce number of NAK received with L1 enabled. - for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { - rwAlink (SB_RCINDXP_REGA0 | portId << 24, 0xFFFFFF0F, 0x10); - } -} - -/** - * CheckGppLinkStatus - loop polling the link status for each GPP port - * - * - * Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -UINT8 -CheckGppLinkStatus ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 retryCounter; - UINT32 portId; - UINT32 abIndex; - UINT32 Data32; - UINT8 portScanMap; - UINT8 portScanMap2; - UINT8 ToggleStatus; - UINT16 i; - SBGPPPORTCONFIG *portCfg; - - - portScanMap = 0; - retryCounter = MAX_TRAINING_RETRY; - ToggleStatus = 0; - - // Obtain a list of ports to be checked - for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { - portCfg = &pConfig->PORTCONFIG[portId].PortCfg; - if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) { - portScanMap |= 1 << portId; - } - } - portScanMap2 = portScanMap; - - // - // After training is enabled, Check LCSTATE for each port, if LCSTATE<= 4, then keep - // polling for up to 40ms. If LCSTATE still <= 4, then assume the port to be empty. - // - i = 400; - while ( --i && portScanMap2) { - for (portId = 0; portId < MAX_GPP_PORTS; portId++) { - portCfg = &pConfig->PORTCONFIG[portId].PortCfg; - if (((portCfg->PortHotPlug == FALSE) || ((portCfg->PortHotPlug == TRUE) && (pConfig->S3Resume == FALSE)) ) && (portScanMap2 & (1 << portId))) { - // - // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P) - // - abIndex = SB_RCINDXP_REGA5 | ((UINT32) RCINDXP << 29) | (portId << 24); - Data32 = readAlink (abIndex) & 0x3F; - if ((UINT8) (Data32) > 4) { - portScanMap2 &= ~(1 << portId); // This port is not empty - break; - } - SbStall (100); // Delay 100us - } - } - } - portScanMap &= ~portScanMap2; // Mark remaining ports as empty - - - while ( --retryCounter && portScanMap ) { - for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { - portCfg = &pConfig->PORTCONFIG[portId].PortCfg; - if (( portCfg->PortHotPlug == TRUE ) && ( pConfig->S3Resume )) { - continue; - } - if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) { - // - // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P) - // - SbStall (1000); // Delay 400us - abIndex = SB_RCINDXP_REGA5 | ((UINT32) RCINDXP << 29) | (portId << 24); - Data32 = readAlink (abIndex) & 0x3F3F3F3F; - - if ( (UINT8) (Data32) == 0x10 ) { - portCfg->PortDetected = TRUE; - portScanMap &= ~(1 << portId); - } else { - for (i = 0; i < 4; i++) { - // - // Compliance mode (0x7), downgrade from Gen2 to Gen1 (*A12) - // - if ((UINT8) (Data32) == 0x29 || (UINT8) (Data32) == 0x2A || (UINT8) (Data32) == 0x7 ) { - ToggleStatus |= (1 << portId); // A11 only: need to toggle GPP reset - portScanMap &= ~(1 << portId); - } - Data32 >>= 8; - } - } - } - } - } - return ToggleStatus; -} - - -/** - * AfterGppLinkInit - * - Search for display device behind each GPP port - * - If the port is empty AND not hotplug-capable: - * * Turn off link training - * * (optional) Power down the port - * * Hide the configuration space (Turn off the port) - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -AfterGppLinkInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 portId; - SBGPPPORTCONFIG *portCfg; - UINT32 regBusNumber; - UINT32 abValue; - UINT32 abIndex; - UINT32 i; - UINT32 Data32; - UINT8 bValue; - UINT8 cimGppGen2; - - cimGppGen2 = pConfig->GppGen2; -#if SB_CIMx_PARAMETER == 0 - cimGppGen2 = cimGppGen2Default; -#endif - - bValue = GPP_EFUSE_LOCATION; - getEfuseStatus (&bValue); - if ( (bValue & GPP_GEN2_EFUSE_BIT) != 0 ) { - cimGppGen2 = FALSE; - } else { - pConfig->CoreGen2Enable = TRUE; // Output for platform use - } - -//GPP Gen2 Speed Change -// if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) { -// PCIe_Cfg 0x88[3:0] = 0x2 -// RCINDP_Reg 0xA2[13] = 0x0 -// RCINDP_Reg 0xC0[15] = 0x0 -// RCINDP_Reg 0xA4[29] = 0x1 -// } else { -// PCIe_Cfg 0x88[3:0] = 0x1 -// RCINDP_Reg 0xA4[0] = 0x0 -// RCINDP_Reg 0xA2[13] = 0x1 -// RCINDP_Reg 0xC0[15] = 0x0 -// RCINDP_Reg 0xA4[29] = 0x1 -// } - for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { - portCfg = &pConfig->PORTCONFIG[portId].PortCfg; - abValue = readAlink (SB_RCINDXP_REGA4 | portId << 24) & BIT0; - if (( cimGppGen2 == TRUE ) && (abValue == BIT0) && (portCfg->PortDetected == TRUE)) { - portCfg->PortIsGen2 = TRUE; // Output for platform use - sbGppForceGen2 (portId); - //_asm {jmp $}; - SbStall (400); // Delay 400us - i = 500; - Data32 = 0; - while ( --i ) { - abIndex = SB_RCINDXP_REGA5 | ((UINT32) RCINDXP << 29) | (portId << 24); - Data32 = readAlink (abIndex) & 0x3F; - if ((UINT8) (Data32) == 0x10) { - break; - } - SbStall (400); // Delay 100us - } - if (!( (UINT8) (Data32) == 0x10 )) { - if (pConfig->GppCompliance == FALSE) { - portCfg->PortIsGen2 = FALSE; // Revert to default; output for platform use - sbGppForceGen1 (portId); - } - } - } else { - if (pConfig->GppCompliance == FALSE) { - sbGppForceGen1 (portId); - } - } -//RPR 5.9 Link Bandwidth Notification Capability Enable -//RCINDC 0xC1[0] = 1 -//PCIe Cfg 0x68[10] = 0 -//PCIe Cfg 0x68[11] = 0 - - rwAlink (SB_RCINDXC_REGC1, 0xFFFFFFFF, BIT0); - RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x68), AccWidthUint16, ~(BIT10 + BIT11), 0); - } - -// Status = AGESA_SUCCESS; - pConfig->GppFoundGfxDev = 0; - abValue = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); - - for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { - portCfg = &pConfig->PORTCONFIG[portId].PortCfg; - // Check if there is GFX device behind each GPP port - if ( portCfg->PortDetected == TRUE ) { - regBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8); - WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, ®BusNumber); - // *** Stall (); - ReadPCI (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccWidthUint8, &bValue); - if ( bValue == 3 ) { - pConfig->GppFoundGfxDev |= (1 << portId); - } - regBusNumber = 0; - WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, ®BusNumber); - } - - // Mask off non-applicable ports - else if ( portCfg->PortPresent == FALSE ) { - abValue &= ~(1 << (portId + 4)); - } - // Mask off empty port if the port is not hotplug-capable - else if ( portCfg->PortHotPlug == FALSE ) { - abValue &= ~(1 << (portId + 4)); - } - // Clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) to make hotplug working - if ( portCfg->PortHotPlug == TRUE ) { - rwAlink ((SB_ABCFG_REG340 + portId * 4) | ((UINT32) ABCFG << 29), ~BIT21, 0); - -// RPR5.12 Hot Plug: PCIe Native Support -// RCINDP_Reg 0x10[3] = 0x1 -// PCIe_Cfg 0x5A[8] = 0x1 -// PCIe_Cfg 0x6C[6] = 0x1 -// RCINDP_Reg 0x20[19] = 0x0 - - rwAlink ((SB_RCINDXP_REG10 | ((UINT32) RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3); - RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x5b), AccWidthUint8, 0xff, BIT0); - RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x6c), AccWidthUint8, 0xff, BIT6); - rwAlink ((SB_RCINDXP_REG20 | ((UINT32) RCINDXP << 29) | (portId << 24)), ~BIT19, 0); - } - } - if ( pConfig->GppUnhidePorts == FALSE ) { - if ((abValue & 0xF0) == 0) { - abValue = BIT8; // if all ports are empty set GPP_RESET - } else if ((abValue & 0xE0) != 0 && (abValue & 0x10) == 0) { - abValue |= BIT4; // PortA should always be visible whenever other ports are exist - } - - // Update GPP_Portx_Enable (abcfg:0xC0[7:5]) - writeAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), abValue); - } - - // - // Common initialization for open GPP ports - // - for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { - ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue); - if (bValue != 0xff) { - // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0]) - bValue &= 0xf0; - bValue |= 0x06; - WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue); - - // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1 - abIndex = SB_RCINDXP_REG70 | ((UINT32) RCINDXP << 29) | (portId << 24); - abValue = readAlink (abIndex) | BIT19; - writeAlink (abIndex, abValue); - - // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0 - abIndex = SB_RCINDXP_REG20 | ((UINT32) RCINDXP << 29) | (portId << 24); - abValue = readAlink (abIndex) & ~BIT19; - writeAlink (abIndex, abValue); - - } - } -} - - -/** - * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sbPcieGppLateInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 reg32Value; - UINT8 portId; - UINT8 busNum; - UINT8 aspmValue; - UINT8 reg8Value; - UINT8 cimGppPhyPllPowerDown; - - reg8Value = 0x01; -// -// Configure ASPM -// -// writeAlink (0xC0 | ((UINT32) RCINDXC << 29), 0x400); // Set STRAP_F0_MSI_EN - aspmValue = (UINT8)pConfig->GppPortAspm; - cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown; -#if SB_CIMx_PARAMETER == 0 - aspmValue = cimGppPortAspmDefault; - cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault; -#endif - - for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) { - // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under Vista - // when native PCIE is enabled but MSI is not available - // SB02029: SB800 BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg - WritePCI (PCI_ADDRESS (0, 21, portId, 0x3d), AccWidthUint8, ®8Value); - ReadPCI (PCI_ADDRESS (0, 21, portId, 0x19), AccWidthUint8, &busNum); - if (busNum != 0xFF) { - ReadPCI (PCI_ADDRESS (busNum, 0, 0, 0x00), AccWidthUint32, ®32Value); - if (reg32Value != 0xffffffff) { - // Set ASPM on EP side - sbGppSetAspm (PCI_ADDRESS (busNum, 0, 0, 0), aspmValue & 0x3); - // Set ASPM on port side - sbGppSetAspm (PCI_ADDRESS (0, 21, portId, 0), aspmValue & 0x3); - } - } - aspmValue = aspmValue >> 2; - } - -// -// Configure Lock HWInit registers -// - reg32Value = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); - if (reg32Value & 0xF0) { - reg32Value = readAlink (SB_RCINDXC_REG10 | ((UINT32) RCINDXC << 29)); - writeAlink (SB_RCINDXC_REG10 | ((UINT32) RCINDXC << 29), reg32Value | BIT0); // Set HWINIT_WR_LOCK - - if ( cimGppPhyPllPowerDown == TRUE ) { -// -// RPR 5.4 Power Saving Feature for GPP Lanes -// - UINT32 abValue; - // Set PCIE_P_CNTL in Alink PCIEIND space - abValue = readAlink (RC_INDXC_REG40 | ((UINT32) RCINDXC << 29)); - abValue |= BIT12 + BIT3 + BIT0; - abValue &= ~(BIT9 + BIT4); - writeAlink (RC_INDXC_REG40 | ((UINT32) RCINDXC << 29), abValue); - } - } - -// -// Configure Lock HWInit registers -// - reg32Value = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); -// -// Disable hidden register decode and serial number capability -// - reg32Value = readAlink (SB_ABCFG_REG330 | ((UINT32) ABCFG << 29)); - writeAlink (SB_ABCFG_REG330 | ((UINT32) ABCFG << 29), reg32Value & ~(BIT26 + BIT10)); -} - -/** - * sbGppSetAspm - Set SPP ASPM - * - * - * @param[in] pciAddress PCI Address. - * @param[in] LxState Lane State. - * - */ -VOID -sbGppSetAspm ( - IN UINT32 pciAddress, - IN UINT8 LxState - ) -{ - UINT8 pcieCapOffset; - UINT8 value8; - UINT8 maxFuncs; - UINT32 devBDF; - - maxFuncs = 1; - ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8); - - if (value8 & BIT7) { - maxFuncs = 8; // multi-function device - } - while (maxFuncs != 0) { - devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16); - pcieCapOffset = sbFindPciCap (devBDF, PCIE_CAP_ID); - if (pcieCapOffset) { - // Read link capabilities register (0x0C[11:10] - ASPM support) - ReadPCI (devBDF + pcieCapOffset + 0x0D, AccWidthUint8, &value8); - if (value8 & BIT2) { - value8 = (value8 >> 2) & (BIT1 + BIT0); - // Set ASPM state in link control register - RWPCI (devBDF + pcieCapOffset + 0x10, AccWidthUint8, 0xffffffff, LxState & value8); - } - } - maxFuncs--; - } -} - -/** - * sbFindPciCap - Find PCI Cap - * - * - * @param[in] pciAddress PCI Address. - * @param[in] targetCapId Target Cap ID. - * - */ -UINT8 -sbFindPciCap ( - IN UINT32 pciAddress, - IN UINT8 targetCapId - ) -{ - UINT8 NextCapPtr; - UINT8 CapId; - - NextCapPtr = 0x34; - while (NextCapPtr != 0) { - ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &NextCapPtr); - if (NextCapPtr == 0xff) { - return 0; - } - if (NextCapPtr != 0) { - ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &CapId); - if (CapId == targetCapId) { - break; - } else { - NextCapPtr++; - } - } - } - return NextCapPtr; -} - -/** - * sbGppForceGen2 - Set SPP to GENII - * - * - * @param[in] portId - * - */ -VOID -sbGppForceGen2 ( - IN UINT32 portId - ) -{ - RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x02); - rwAlink (SB_RCINDXP_REGA2 | portId << 24, ~BIT13, 0); - rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0); - rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29); -} - -/** - * sbGppForceGen1 - Set SPP to GENI - * - * - * @param[in] portId - * - */ -VOID -sbGppForceGen1 ( - IN UINT32 portId - ) -{ - RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x01); - rwAlink (SB_RCINDXP_REGA4 | portId << 24, ~BIT0, 0); - rwAlink (SB_RCINDXP_REGA2 | portId << 24, 0xFFFFFFFF, BIT13); - rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0); - rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29); -} - -/** - * sbGppDisableUnusedPadMap - Return GPP Pad Map - * - * - * @param[in] pConfig - * - */ -VOID -sbGppDisableUnusedPadMap ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 Data32; - UINT32 HoldData32; - SBGPPPORTCONFIG *portCfg; - UINT8 cimGppLaneReversal; - UINT8 cimAlinkPhyPllPowerDown; - UINT8 cimGppPhyPllPowerDown; - - cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown; - cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal; - cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown; -#if SB_CIMx_PARAMETER == 0 - cimGppLaneReversal = cimGppLaneReversalDefault; - cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault; - cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault; -#endif - - Data32 = 0; - HoldData32 = 0; - switch ( pConfig->GppLinkConfig ) { - case GPP_CFGMODE_X4000: - portCfg = &pConfig->PORTCONFIG[0].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= 0x0f0f; - HoldData32 |= 0x1000; - } - break; - case GPP_CFGMODE_X2200: - portCfg = &pConfig->PORTCONFIG[0].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303; - HoldData32 |= 0x1000; - } - portCfg = &pConfig->PORTCONFIG[1].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0303:0x0c0c; - HoldData32 |= 0x2000; - } - break; - case GPP_CFGMODE_X2110: - portCfg = &pConfig->PORTCONFIG[0].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303; - HoldData32 |= 0x1000; - } - portCfg = &pConfig->PORTCONFIG[1].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404; - HoldData32 |= 0x2000; - } - portCfg = &pConfig->PORTCONFIG[2].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808; - HoldData32 |= 0x4000; - } - break; - case GPP_CFGMODE_X1111: - portCfg = &pConfig->PORTCONFIG[0].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0808:0x0101; - HoldData32 |= 0x1000; - } - portCfg = &pConfig->PORTCONFIG[1].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0404:0x0202; - HoldData32 |= 0x2000; - } - portCfg = &pConfig->PORTCONFIG[2].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404; - HoldData32 |= 0x4000; - } - portCfg = &pConfig->PORTCONFIG[3].PortCfg; - if ( portCfg->PortDetected == FALSE ) { - Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808; - HoldData32 |= 0x8000; - } - break; - default: - break; - } - -// RPR 5.11 Power Saving With GPP Disable -// ABCFG 0xC0[8] = 0x0 -// ABCFG 0xC0[15:12] = 0xF -// Enable "Power Saving Feature for A-Link Express Lanes" -// Enable "Power Saving Feature for GPP Lanes" -// ABCFG 0x90[19] = 1 -// ABCFG 0x90[6] = 1 -// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF -// ABCFG 0xC0[7:4] = 0x0 - if ( (Data32 & 0xf) == 0xf ) Data32 |= 0x0cff0000; - if ( cimAlinkPhyPllPowerDown && cimGppPhyPllPowerDown ) { - rwAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), ~BIT8, 0); - rwAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29), 0xFFFFFFFF, HoldData32); - rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); - rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12)); - rwAlink ((SB_ABCFG_REG90 | ((UINT32) ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19)); - rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, Data32); - } -} diff --git a/src/vendorcode/amd/cimx/sb800/IOLIB.c b/src/vendorcode/amd/cimx/sb800/IOLIB.c deleted file mode 100644 index 1d21d9cb2b..0000000000 --- a/src/vendorcode/amd/cimx/sb800/IOLIB.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - - -VOID -ReadIO ( - IN UINT16 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - switch ( OpFlag ) { - case AccWidthUint8: - *(UINT8*)Value = ReadIo8 (Address); - break; - case AccWidthUint16: - *(UINT16*)Value = ReadIo16 (Address); - break; - case AccWidthUint32: - *(UINT32*)Value = ReadIo32 (Address); - break; - } -} - -VOID -WriteIO ( - IN UINT16 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - switch ( OpFlag ) { - case AccWidthUint8: - WriteIo8 (Address, *(UINT8*)Value); - break; - case AccWidthUint16: - WriteIo16 (Address, *(UINT16*)Value); - break; - case AccWidthUint32: - WriteIo32 (Address, *(UINT32*)Value); - break; - } -} - -VOID -RWIO ( - IN UINT16 Address, - IN UINT8 OpFlag, - IN UINT32 Mask, - IN UINT32 Data - ) -{ - UINT32 Result; - ReadIO (Address, OpFlag, &Result); - Result = (Result & Mask) | Data; - WriteIO (Address, OpFlag, &Result); -} diff --git a/src/vendorcode/amd/cimx/sb800/LEGACY.c b/src/vendorcode/amd/cimx/sb800/LEGACY.c deleted file mode 100644 index f95006feb8..0000000000 --- a/src/vendorcode/amd/cimx/sb800/LEGACY.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -UINT32 -GetFixUp ( - OUT VOID - ) -{ - AMD_CONFIG_PARAMS* Result; - Result = (AMD_CONFIG_PARAMS*) getConfigPointer (); - if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) { - return 0; - } - return Result->ImageBasePtr; -} diff --git a/src/vendorcode/amd/cimx/sb800/MEMLIB.c b/src/vendorcode/amd/cimx/sb800/MEMLIB.c deleted file mode 100644 index d9eb8fff38..0000000000 --- a/src/vendorcode/amd/cimx/sb800/MEMLIB.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -VOID -ReadMEM ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - switch ( OpFlag ) { - case AccWidthUint8: - *((UINT8*)Value) = *((UINT8*) ((UINTN)Address)); - break; - case AccWidthUint16: - *((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); - break; - case AccWidthUint32: - *((UINT32*)Value) = *((UINT32*) ((UINTN)Address)); - break; - } -} - -VOID -WriteMEM ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - switch ( OpFlag ) { - case AccWidthUint8 : - *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value); - break; - case AccWidthUint16: - *((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); - break; - case AccWidthUint32: - *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value); - break; - } -} - -VOID -RWMEM ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN UINT32 Mask, - IN UINT32 Data - ) -{ - UINT32 Result; - ReadMEM (Address, OpFlag, &Result); - Result = (Result & Mask) | Data; - WriteMEM (Address, OpFlag, &Result); -} - - diff --git a/src/vendorcode/amd/cimx/sb800/Makefile.inc b/src/vendorcode/amd/cimx/sb800/Makefile.inc deleted file mode 100644 index 8eb72fab29..0000000000 --- a/src/vendorcode/amd/cimx/sb800/Makefile.inc +++ /dev/null @@ -1,57 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -CPPFLAGS_x86_32 += -I$(src)/southbridge/amd/cimx/sb800 -CPPFLAGS_x86_32 += -I$(src)/vendorcode/amd/cimx/sb800 - -CPPFLAGS_x86_64 += -I$(src)/southbridge/amd/cimx/sb800 -CPPFLAGS_x86_64 += -I$(src)/vendorcode/amd/cimx/sb800 - -romstage-y += ACPILIB.c -romstage-y += AZALIA.c -romstage-y += DISPATCHER.c -romstage-y += ECfanc.c -romstage-y += ECfanLIB.c -romstage-y += GEC.c -romstage-y += Gpp.c -romstage-y += PMIO2LIB.c -romstage-y += SATA.c -romstage-y += SBCMN.c -romstage-y += SBMAIN.c -romstage-y += SBPort.c -romstage-y += MEMLIB.c -romstage-y += PCILIB.c -romstage-y += IOLIB.c -romstage-y += PMIOLIB.c -romstage-y += AMDLIB.c -romstage-y += SBPELIB.c -romstage-y += AMDSBLIB.c -romstage-y += ECLIB.c -romstage-y += EC.c -romstage-y += SMM.c -romstage-y += USB.c - -ramstage-y += ACPILIB.c -ramstage-y += AZALIA.c -ramstage-y += DISPATCHER.c -ramstage-y += ECfanc.c -ramstage-y += ECfanLIB.c -ramstage-y += GEC.c -ramstage-y += Gpp.c -ramstage-y += PMIO2LIB.c -ramstage-y += SATA.c -ramstage-y += SBCMN.c -ramstage-y += SBMAIN.c -ramstage-y += SBPort.c -ramstage-y += MEMLIB.c -ramstage-y += PCILIB.c -ramstage-y += IOLIB.c -ramstage-y += PMIOLIB.c -ramstage-y += AMDLIB.c -ramstage-y += SBPELIB.c -ramstage-y += AMDSBLIB.c -ramstage-y += ECLIB.c -ramstage-y += EC.c -ramstage-y += SMM.c -ramstage-y += USB.c -#ramstage-y += LEGACY.c -#ramstage-y += SbModInf.c diff --git a/src/vendorcode/amd/cimx/sb800/OEM.h b/src/vendorcode/amd/cimx/sb800/OEM.h deleted file mode 100644 index c184c657ca..0000000000 --- a/src/vendorcode/amd/cimx/sb800/OEM.h +++ /dev/null @@ -1,313 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef BIOS_SIZE - #define BIOS_SIZE 0x04 //04 - 1MB -#endif -#ifndef LEGACY_FREE - #define LEGACY_FREE 0x00 -#endif -//#define ACPI_SLEEP_TRAP 0x01 -//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01 - -/** - * Module Specific Defines for platform BIOS - * - */ - -/** - * PCIEX_BASE_ADDRESS - Define PCIE base address - * - * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000 - */ -#ifdef MOVE_PCIEBAR_TO_F0000000 - #define PCIEX_BASE_ADDRESS 0xF7000000 -#else - #define PCIEX_BASE_ADDRESS CONFIG_ECAM_MMCONF_BASE_ADDRESS -#endif - -/** - * SMBUS0_BASE_ADDRESS - Smbus base address - * - */ -#ifndef SMBUS0_BASE_ADDRESS - #define SMBUS0_BASE_ADDRESS 0xB00 -#endif - -/** - * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address - * - */ -#ifndef SMBUS1_BASE_ADDRESS - #define SMBUS1_BASE_ADDRESS 0xB20 -#endif - -/** - * GEC_BASE_ADDRESS - Gec Shadow ROM base address - * - */ -#ifndef GEC_BASE_ADDRESS - #define GEC_BASE_ADDRESS 0xFED61000 -#endif - - -/** - * SIO_PME_BASE_ADDRESS - Super IO PME base address - * - */ -#ifndef SIO_PME_BASE_ADDRESS - #define SIO_PME_BASE_ADDRESS 0xE00 -#endif - -/** - * SIO_HWM_BASE_ADDRESS - Super IO HWM base address - * - */ -#ifndef SIO_HWM_BASE_ADDRESS - #define SIO_HWM_BASE_ADDRESS 0x290 -#endif - -/** - * SPI_BASE_ADDRESS - SPI controller (ROM) base address - * - */ -#ifndef SPI_BASE_ADDRESS - #define SPI_BASE_ADDRESS 0xFEC10000 -#endif - -/** - * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address - * - */ -#ifndef WATCHDOG_TIMER_BASE_ADDRESS - #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address -#endif - -/** - * HPET_BASE_ADDRESS - HPET base address - * - */ -#ifndef HPET_BASE_ADDRESS - #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address -#endif - -/** - * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address - * - */ -#ifdef ALT_ADDR_400 - #define ACPI_BLK_BASE 0x400 -#else - #define ACPI_BLK_BASE 0x800 -#endif - -#define PM1_STATUS_OFFSET 0x00 -#define PM1_ENABLE_OFFSET 0x02 -#define PM1_CONTROL_OFFSET 0x04 -#define PM_TIMER_OFFSET 0x08 -#define CPU_CONTROL_OFFSET 0x10 -#define EVENT_STATUS_OFFSET 0x20 -#define EVENT_ENABLE_OFFSET 0x24 - -/** - * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address - * - */ -#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr - -/** - * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address - * - */ -#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr - -/** - * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address - * - */ -#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr - -/** - * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address - * - */ -#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr - -/** - * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address - * - */ -#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr - -/** - * SMI_CMD_PORT - ACPI SMI Command block base address - * - */ -#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr - -/** - * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address - * - */ -#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr - -/** - * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID. - * Define value for SSID while SATA controller set to IDE mode. - */ -#ifndef SATA_IDE_MODE_SSID - #define SATA_IDE_MODE_SSID 0x43901002 -#endif - -/** - * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID. - * Define value for SSID while SATA controller set to RAID mode. - */ -#ifndef SATA_RAID_MODE_SSID - #define SATA_RAID_MODE_SSID 0x43921002 -#endif - -/** - * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID. - * Define value for SSID while SATA controller set to RAID5 mode. - */ -#ifndef SATA_RAID5_MODE_SSID - #define SATA_RAID5_MODE_SSID 0x43931002 -#endif - -/** - * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID. - * Define value for SSID while SATA controller set to AHCI mode. - */ -#ifndef SATA_AHCI_SSID - #define SATA_AHCI_SSID 0x43911002 -#endif - -/** - * OHCI_SSID - All SB OHCI controllers SSID value. - * - */ -#ifndef OHCI_SSID - #define OHCI_SSID 0x43971002 -#endif - -/** - * EHCI_SSID - All SB EHCI controllers SSID value. - * - */ -#ifndef EHCI_SSID - #define EHCI_SSID 0x43961002 -#endif - -/** - * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value. - * - */ -#ifndef OHCI4_SSID - #define OHCI4_SSID 0x43991002 -#endif - -/** - * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value. - * - */ -#ifndef SMBUS_SSID - #define SMBUS_SSID 0x43851002 -#endif - -/** - * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value. - * - */ -#ifndef IDE_SSID - #define IDE_SSID 0x439C1002 -#endif - -/** - * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value. - * - */ -#ifndef AZALIA_SSID - #define AZALIA_SSID 0x43831002 -#endif - -/** - * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value. - * - */ -#ifndef LPC_SSID - #define LPC_SSID 0x439D1002 -#endif - -/** - * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value. - * - */ -#ifndef PCIB_SSID - #define PCIB_SSID 0x43841002 -#endif - -/** - * USB_PLL_Voltage - CG2 Clock voltage setting. - * - */ -#ifndef USB_PLL_Voltage - #define USB_PLL_Voltage 0x10 -#endif - -/** - * USB_RX_MODE - Enable CG2 clock voltage setting. - * - */ -#ifndef USB_RX_MODE - #define USB_RX_MODE 0x01 -#endif - -/** - * Spread_Spectrum_Type - * - * - 0 : Normal platform - * - 1 : Ontario platform - */ -#ifndef Spread_Spectrum_Type - #define Spread_Spectrum_Type 0x00 -#endif - -/** - * Imc Enable OverWrite - * 2 - by default strapping - * 1 - On - * 0 - Off - */ -#ifndef IMC_ENABLE_OVER_WRITE - #define IMC_ENABLE_OVER_WRITE 0x02 -#endif diff --git a/src/vendorcode/amd/cimx/sb800/PCILIB.c b/src/vendorcode/amd/cimx/sb800/PCILIB.c deleted file mode 100644 index c34c5b0dc9..0000000000 --- a/src/vendorcode/amd/cimx/sb800/PCILIB.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -VOID -ReadPCI ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - - if ( (UINT16)Address < 0xff ) { - //Normal Config Access - UINT32 AddrCf8; - AddrCf8 = (1U << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC); - WriteIO (0xCf8, AccWidthUint32, &AddrCf8); - ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); - } -} - -VOID -WritePCI ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - OpFlag = OpFlag & 0x7f; - if ( (UINT16)Address < 0xff ) { - //Normal Config Access - UINT32 AddrCf8; - AddrCf8 = (1U << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC); - WriteIO (0xCf8, AccWidthUint32, &AddrCf8); - WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value); - } -} - -VOID -RWPCI ( - IN UINT32 Address, - IN UINT8 OpFlag, - IN UINT32 Mask, - IN UINT32 Data - ) -{ - UINT32 Result; - Result = 0; - OpFlag = OpFlag & 0x7f; - ReadPCI (Address, OpFlag, &Result); - Result = (Result & Mask) | Data; - WritePCI (Address, OpFlag, &Result); -} diff --git a/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c b/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c deleted file mode 100644 index 82864e695a..0000000000 --- a/src/vendorcode/amd/cimx/sb800/PMIO2LIB.c +++ /dev/null @@ -1,130 +0,0 @@ -/** - * @file - * - * Southbridge PMIO2 access common routine - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PMIO2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Read Data Buffer - * - */ -VOID -ReadPMIO2 ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - UINT8 i; - OpFlag = OpFlag & 0x7f; - - if ( OpFlag == 0x02 ) { - OpFlag = 0x03; - } - for ( i = 0; i <= OpFlag; i++ ) { - WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 - Address++; - ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i); // SB_IOMAP_REGCD1 - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PMIO 2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Write Data Buffer - * - */ -VOID -WritePMIO2 ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - UINT8 i; - OpFlag = OpFlag & 0x7f; - - if ( OpFlag == 0x02 ) { - OpFlag = 0x03; - } - for ( i = 0; i <= OpFlag; i++ ) { - WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0 - Address++; - WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1 - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * RWPMIO2 - Read/Write PMIO2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] AndMask - Data And Mask 32 bits - * @param[in] OrMask - Data OR Mask 32 bits - * - */ -VOID -RWPMIO2 ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN UINT32 AndMask, - IN UINT32 OrMask - ) -{ - UINT32 Result; - OpFlag = OpFlag & 0x7f; - ReadPMIO2 (Address, OpFlag, &Result); - Result = (Result & AndMask) | OrMask; - WritePMIO2 (Address, OpFlag, &Result); -} diff --git a/src/vendorcode/amd/cimx/sb800/PMIOLIB.c b/src/vendorcode/amd/cimx/sb800/PMIOLIB.c deleted file mode 100644 index 6cce4f1b50..0000000000 --- a/src/vendorcode/amd/cimx/sb800/PMIOLIB.c +++ /dev/null @@ -1,129 +0,0 @@ -/** - * @file - * - * Southbridge PMIO access common routine - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -/*----------------------------------------------------------------------------------------*/ -/** - * Read PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Read Data Buffer - * - */ -VOID -ReadPMIO ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - UINT8 i; - OpFlag = OpFlag & 0x7f; - - if ( OpFlag == 0x02 ) { - OpFlag = 0x03; - } - for ( i = 0; i <= OpFlag; i++ ) { - WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 - Address++; - ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7 - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Write PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Write Data Buffer - * - */ -VOID -WritePMIO ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN VOID* Value - ) -{ - UINT8 i; - OpFlag = OpFlag & 0x7f; - - if ( OpFlag == 0x02 ) { - OpFlag = 0x03; - } - for ( i = 0; i <= OpFlag; i++ ) { - WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6 - Address++; - WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7 - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * RWPMIO - Read/Write PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] AndMask - Data And Mask 32 bits - * @param[in] OrMask - Data OR Mask 32 bits - * - */ -VOID -RWPMIO ( - IN UINT8 Address, - IN UINT8 OpFlag, - IN UINT32 AndMask, - IN UINT32 OrMask - ) -{ - UINT32 Result; - OpFlag = OpFlag & 0x7f; - ReadPMIO (Address, OpFlag, &Result); - Result = (Result & AndMask) | OrMask; - WritePMIO (Address, OpFlag, &Result); -} diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c deleted file mode 100644 index f9823d8fb5..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ /dev/null @@ -1,675 +0,0 @@ - -/** - * @file - * - * Config Southbridge SATA controller - * - * Init SATA features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -// -// Declaration of local functions -// -VOID sataSetIrqIntResource (IN AMDSBCFG* pConfig); -VOID sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5); -VOID shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5); -VOID sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5); - -/** - * sataSetIrqIntResource - Config SATA IRQ/INT# resource - * - * - * - Private function - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sataSetIrqIntResource ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 dbValue; - // IRQ14/IRQ15 come from IDE or SATA - dbValue = 0x08; - WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); - ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); - dbValue = dbValue & 0x0F; - if (pConfig->SataClass == 3) { - dbValue = dbValue | 0x50; - } else { - if (pConfig->SataIdeMode == 1) { - // Both IDE & SATA set to Native mode - dbValue = dbValue | 0xF0; - } - } - WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); -} - -/** - * sataBar5setting - Config SATA BAR5 - * - * - Private function - * - * @param[in] pConfig - Southbridge configuration structure pointer. - * @param[in] *pBar5 - SATA BAR5 buffer. - * - */ -VOID -sataBar5setting ( - IN AMDSBCFG* pConfig, - IN UINT32 *pBar5 - ) -{ - //Get BAR5 value - ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5); - //Assign temporary BAR if is not already assigned - if ( (*pBar5 == 0) || (*pBar5 == - 1) ) { - //assign temporary BAR5 - if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) { - *pBar5 = 0xFEC01000; - } else { - *pBar5 = pConfig->TempMMIO; - } - WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5); - } - //Clear Bits 9:0 - *pBar5 = *pBar5 & 0xFFFFFC00; -} -/** - * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock - * - * - Private function - * - * @param[in] pConfig Southbridge configuration structure pointer. - * @param[in] ddBar5 Sata BAR5 base address. - * - */ -VOID -shutdownUnconnectedSataPortClock ( - IN AMDSBCFG* pConfig, - IN UINT32 ddBar5 - ) -{ - UINT8 dbPortNum; - UINT8 dbPortSataStatus; - UINT8 NumOfPorts; - UINT8 cimSataClkAutoOff; - - cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff; -#if SB_CIMx_PARAMETER == 0 - cimSataClkAutoOff = cimSataClkAutoOffDefault; -#endif - NumOfPorts = 0; - if ( cimSataClkAutoOff == TRUE ) { - for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) { - ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus); - // Shutdown the clock for the port and do the necessary port reporting changes. - // ?? Error port status should be 1 not 3 - if ( ((dbPortSataStatus & 0x0F) != 0x03) && (! ((pConfig->SataEspPort) & (1 << dbPortNum))) ) { - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum)); - RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00); - } - } //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++) - ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); - //if all ports are in disabled state, report atleast one port - if ( (dbPortSataStatus & 0x3F) == 0) { - RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0x3F), 01); - } - ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus); - for (dbPortNum = 0; dbPortNum < 6; dbPortNum ++) { - if (dbPortSataStatus & (1 << dbPortNum)) { - NumOfPorts++; - } - } - if ( NumOfPorts == 0) { - NumOfPorts = 0x01; - } - RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1); - } //end of SataClkAuto Off option -} - -/** - * Table for class code of SATA Controller in different modes - * - * - * - * - */ -static const UINT32 sataIfCodeTable[] = -{ - 0x01018F40, //sata class ID of IDE - 0x01040040, //sata class ID of RAID - 0x01060140, //sata class ID of AHCI - 0x01018A40, //sata class ID of Legacy IDE - 0x01018F40, //sata class ID of IDE to AHCI mode -}; - -/** - * Table for device id of SATA Controller in different modes - * - * - * - * - */ -static const UINT16 sataDeviceIDTable[] = -{ - 0x4390, //sata device ID of IDE - 0x4392, //sata device ID of RAID - 0x4391, //sata class ID of AHCI - 0x4390, //sata device ID of Legacy IDE - 0x4390, //sata device ID of IDE->AHCI mode -}; - -/** - * Table for Sata Phy Fine Setting - * - * - * - * - */ -static const SATAPHYSETTING sataPhyTable[] = -{ - {0x3006, 0x0056A607}, - {0x2006, 0x00061400}, - {0x1006, 0x00061302}, - - {0x3206, 0x0056A607}, - {0x2206, 0x00061400}, - {0x1206, 0x00061302}, - - {0x3406, 0x0056A607}, - {0x2406, 0x00061402}, - {0x1406, 0x00064300}, - - {0x3606, 0x0056A607}, - {0x2606, 0x00061402}, - {0x1606, 0x00064300}, - - {0x3806, 0x0056A700}, - {0x2806, 0x00061502}, - {0x1806, 0x00064302}, - - {0x3A06, 0x0056A700}, - {0x2A06, 0x00061502}, - {0x1A06, 0x00064302} -}; - -/** - * sataInitBeforePciEnum - Config SATA controller before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sataInitBeforePciEnum ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddTempVar; - UINT32 ddValue; - UINT32 *tempptr; - UINT16 *pDeviceIdptr; - UINT32 dwDeviceId; - UINT8 dbValue; - UINT8 pValue; - UINT16 i; - SATAPHYSETTING *pPhyTable; - - ddTempVar = 0; - // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h - // BIT4: Disable fast boot - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4); - // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h - RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SataPortPower); - dbValue = (UINT8)pConfig->SataClass; - if (dbValue == AHCI_MODE_4394) { - dbValue = AHCI_MODE; - } - if (dbValue == IDE_TO_AHCI_MODE_4394) { - dbValue = IDE_TO_AHCI_MODE; - } - // Disable PATA MSI - RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00); - RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00); - - // Get the appropriate class code from the table and write it to PCI register 08h-0Bh - // Set the appropriate SATA class based on the input parameters - // SATA IDE Controller Class ID & SSID - tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]); - if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) { - ddValue = tempptr[0]; - // Write the class code to IDE PCI register 08h-0Bh - RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); - } - ddValue = tempptr[dbValue]; - // Write the class code to SATA PCI register 08h-0Bh - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue); - if ( pConfig->SataClass == LEGACY_IDE_MODE ) { - //Set PATA controller to native mode - RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F); - } - if (pConfig->BuildParameters.IdeSsid != 0 ) { - RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid); - } - // SATA Controller Class ID & SSID - pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]); - if ( pConfig->BuildParameters.SataIDESsid != 0 ) { - ddTempVar = pConfig->BuildParameters.SataIDESsid; - } - dwDeviceId = pDeviceIdptr[dbValue]; - if ( pConfig->SataClass == RAID_MODE) { - if ( pConfig->BuildParameters.SataRAID5Ssid != 0 ) { - ddTempVar = pConfig->BuildParameters.SataRAID5Ssid; - } - dwDeviceId = V_SB_SATA_RAID5_DID; - pValue = SATA_EFUSE_LOCATION; - getEfuseStatus (&pValue); - if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) { - dwDeviceId = V_SB_SATA_RAID_DID; - if ( pConfig->BuildParameters.SataRAIDSsid != 0 ) { - ddTempVar = pConfig->BuildParameters.SataRAIDSsid; - } - } - } - if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) || - ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) { - if ( pConfig->BuildParameters.SataAHCISsid != 0 ) { - ddTempVar = pConfig->BuildParameters.SataAHCISsid; - } - } - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId); - if ( ddTempVar != 0 ) { - RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar); - } - // SATA IRQ Resource - sataSetIrqIntResource (pConfig); - - // 8.4 SATA PHY Programming Sequence - pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]); - for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) { - RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84, AccWidthUint16 | S3_SAVE, ~(BIT1 + BIT2 + BIT9 + BIT10 + BIT11 + BIT12 + BIT13 + BIT14), pPhyTable->wPhyCoreControl); - RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune); - ++pPhyTable; - } - -// CallBackToOEM (SATA_PHY_PROGRAMMING, NULL, pConfig); - - RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); - // Disable write access to PCI header - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); -} - -/** - * sataInitAfterPciEnum - Config SATA controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sataInitAfterPciEnum ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddAndMask; - UINT32 ddOrMask; - UINT32 ddBar5; - UINT8 dbVar; - UINT8 dbPortNum; - UINT8 dbEfuse; - UINT8 dbPortMode; - UINT16 SataPortMode; - UINT8 cimSataAggrLinkPmCap; - UINT8 cimSataPortMultCap; - UINT8 cimSataPscCap; - UINT8 cimSataSscCap; - UINT8 cimSataFisBasedSwitching; - UINT8 cimSataCccSupport; - - cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap; - cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap; - cimSataPscCap = (UINT8) pConfig->SataPscCap; - cimSataSscCap = (UINT8) pConfig->SataSscCap; - cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching; - cimSataCccSupport = (UINT8) pConfig->SataCccSupport; - -#if SB_CIMx_PARAMETER == 0 - cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault; - cimSataPortMultCap = cimSataPortMultCapDefault; - cimSataPscCap = cimSataPscCapDefault; - cimSataSscCap = cimSataSscCapDefault; - cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault; - cimSataCccSupport = cimSataCccSupportDefault; -#endif - - ddAndMask = 0; - ddOrMask = 0; - ddBar5 = 0; - if ( pConfig->SATAMODE.SataMode.SataController == 0 ) { - return; //return if SATA controller is disabled. - } - - //Enable write access to pci header, pm capabilities - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0); - //Disable AHCI Prefetch function - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0x7F, BIT7); - - sataBar5setting (pConfig, &ddBar5); - - ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable - dbEfuse = SATA_FIS_BASE_EFUSE_LOC; - getEfuseStatus (&dbEfuse); - - if ( !cimSataPortMultCap ) { - ddAndMask |= BIT12; - } - if ( cimSataAggrLinkPmCap ) { - ddOrMask |= BIT11; - } else { - ddAndMask |= BIT11; - } - if ( cimSataPscCap ) { - ddOrMask |= BIT1; - } - if ( cimSataSscCap ) { - ddOrMask |= BIT26; - } - if ( cimSataFisBasedSwitching ) { - if (dbEfuse & BIT1) { - ddAndMask |= BIT10; - } else { - ddOrMask |= BIT10; - } - } else { - ddAndMask |= BIT10; - } - // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. - if ( cimSataCccSupport ) { - ddOrMask |= BIT19; - } else { - ddAndMask |= BIT19; - } - RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask); - - - // SATA ESP port setting - // These config bits are set for SATA driver to identify which ports are external SATA ports and need to - // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will - // not enable power management (HIPM & DIPM) for these ports. - if ( pConfig->SataEspPort != 0 ) { - RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0); - RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT12 + BIT13 + BIT14 + BIT15 + BIT16 + BIT17 + BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), (pConfig->SataEspPort << 12)); - // RPR 8.7 External SATA Port Indication Registers - // If any of the ports was programmed as an external port, HCAP.SXS should also be set - RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20); - } else { - // RPR 8.7 External SATA Port Indication Registers - // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port) - RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x00); - RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00); - } - if ( cimSataFisBasedSwitching ) { - if (dbEfuse & BIT1) { - RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00); - } else { - RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), (BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27)); - } - } else { - RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00); - } - - // Disabled SATA MSI and D3 Power State capability - // RPR 8.13 SATA MSI and D3 Power State Capability - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70); - - if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { - // RAID or AHCI - if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) { - RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); - RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); - // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. - // 8 messages - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1); - } else { - // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. - if ( pConfig->SataCccSupport ) { - // 8 messages - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1); - } else { - // 4 messages - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2); - } - } - } - - if ( pConfig->BIOSOSHandoff == 1 ) { - RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0); - } else { - RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00); - } - - SataPortMode = (UINT16)pConfig->SataPortMode; - dbPortNum = 0; - while ( dbPortNum < 6 ) { - dbPortMode = (UINT8) (SataPortMode & 3); - if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) { - if ( dbPortMode == BIT0 ) { - // set GEN 1 - RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10); - } - if ( dbPortMode == BIT1 ) { - // set GEN2 (default is GEN3) - RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20); - } - RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01); - } - SataPortMode >>= 2; - dbPortNum ++; - } - SbStall (1000); - SataPortMode = (UINT16)pConfig->SataPortMode; - dbPortNum = 0; - while ( dbPortNum < 6 ) { - dbPortMode = (UINT8) (SataPortMode & 3); - if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) { - RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00); - } - dbPortNum ++; - SataPortMode >>= 2; - } - WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); - //Disable write access to pci header, pm capabilities - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); -} - - -/** - * sataInitMidPost - Config SATA controller in Middle POST. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sataInitMidPost ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddBar5; - sataBar5setting (pConfig, &ddBar5); - //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround. - if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) { - sataDriveDetection (pConfig, &ddBar5); - } -} - -/** - * sataDriveDetection - Sata drive detection - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * @param[in] *pBar5 Sata BAR5 base address. - * - */ -VOID -sataDriveDetection ( - IN AMDSBCFG* pConfig, - IN UINT32 *pBar5 - ) -{ - UINT32 ddVar0; - UINT8 dbPortNum; - UINT8 dbVar0; - UINT16 dwIoBase; - UINT32 dwVar0; - if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) { - for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) { - ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0); - if ( ( ddVar0 & 0x0F ) == 0x03 ) { - if ( dbPortNum & BIT0 ) { - //this port belongs to secondary channel - ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase); - } else { - //this port belongs to primary channel - ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase); - } - //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them - if ( pConfig->SataClass == LEGACY_IDE_MODE ) { - dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) ); - } - if ( dbPortNum & BIT1 ) { - //this port is slave - dbVar0 = 0xB0; - } else { - //this port is master - dbVar0 = 0xA0; - } - dwIoBase &= 0xFFF8; - WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0); - //Wait in loop for 30s for the drive to become ready - for ( dwVar0 = 0; dwVar0 < 300000; dwVar0++ ) { - ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0); - if ( (dbVar0 & 0x88) == 0 ) { - break; - } - SbStall (100); - } - } //end of if ( ( ddVar0 & 0x0F ) == 0x03) - } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++) - } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)) -} - -/** - * sataInitLatePost - Prepare SATA controller to boot to OS. - * - * - Set class ID to AHCI (if set to AHCI * Mode) - * - Enable AHCI interrupt - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sataInitLatePost ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddBar5; - UINT8 dbVar; - UINT8 dbPortNum; - - //Return immediately is sata controller is not enabled - if ( pConfig->SATAMODE.SataMode.SataController == 0 ) { - return; - } - //Enable write access to pci header, pm capabilities - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); - -// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == SATA_IDE_COMBINE_DISABLE) { - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); -// } - sataBar5setting (pConfig, &ddBar5); - - ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar); - //Enable memory and io access - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03); - - shutdownUnconnectedSataPortClock (pConfig, ddBar5); - - if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) { - //program the AHCI class code - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100); - //Set interrupt enable bit - RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1); - //program the correct device id for AHCI mode - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391); - } - - if (( pConfig->SataClass == AHCI_MODE_4394 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) { - //program the correct device id for AHCI 4394 mode - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4394); - } - - //Clear error status ?? only 4 port - RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF); - //Restore memory and io access bits - WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar ); - //Disable write access to pci header and pm capabilities - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0); - for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) { - RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00); - } -} - - diff --git a/src/vendorcode/amd/cimx/sb800/SB800.h b/src/vendorcode/amd/cimx/sb800/SB800.h deleted file mode 100644 index 861a770c4e..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SB800.h +++ /dev/null @@ -1,1902 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#pragma pack (push, 1) - -#define CIMX_SB_REVISION "1.1.0.6" -#define CIMX_SB_ID "SB80A13" -#ifndef SBCIMx_Version - #define SBCIMx_Version 0x1106 -#endif //CIMx_Version - - -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_POWERON_INIT_Page SB_POWERON_INIT - * @section SB_POWERON_INIT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_POWERON_INIT_CallIn Call Prototype - * @par - * sbPowerOnInit ((AMDSBCFG*) pConfig) (Followed PH Interface) - * @subsection SB_BEFORE_PCI_INIT_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_POWERON_INIT --> 0x00010001 </TD></TR> - * </TABLE> - * @subsection SB_POWERON_INIT_CallOut Prepare for Callout - * @par - * Not Applicable (Not necessary for the current implementation) - * @subsection SB_POWERON_INIT_Config Prepare for Configuration Data. - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> BUILDPARAM::BiosSize </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::LegacyFree </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::EcKbd </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::WatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::GecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::CpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * </TABLE> - * - */ -#define SB_POWERON_INIT 0x00010001 -#define OUTDEBUG_PORT 0x00010002 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_BEFORE_PCI_INIT_Page SB_BEFORE_PCI_INIT - * @section SB_BEFORE_PCI_INIT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_BEFORE_PCI_INIT_CallIn Call Prototype - * @par - * sbBeforePciInit ((AMDSBCFG*)pConfig) (Followed PH Interface) - * @subsection SB_BEFORE_PCI_INIT_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_INIT --> 0x00010010 </TD></TR> - * </TABLE> - * @subsection SB_BEFORE_PCI_INIT_CallOut Prepare for Callout - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR> - * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR> - * </TABLE> - * @subsection SB_BEFORE_PCI_INIT_Config Prepare for Configuration Data. - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * </TABLE> - * - */ -#define SB_BEFORE_PCI_INIT 0x00010010 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_AFTER_PCI_INIT_Page SB_AFTER_PCI_INIT - * @section SB_AFTER_PCI_INIT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_AFTER_PCI_INIT_CallIn Call Prototype - * @par - * sbAfterPciInit ((AMDSBCFG*)pConfig) (Followed PH Interface) - * @subsection SB_AFTER_PCI_INIT_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_AFTER_PCI_INIT --> 0x00010020 </TD></TR> - * </TABLE> - * @subsection SB_AFTER_PCI_INIT_CallOut Prepare for Callout - * @par - * Not Applicable (Not necessary for the current implementation) - * @subsection SB_AFTER_PCI_INIT_Config Prepare for Configuration Data. - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * </TABLE> - * - */ -#define SB_AFTER_PCI_INIT 0x00010020 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_MID_POST_INIT_Page SB_MID_POST_INIT - * @section SB_MID_POST_INIT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_MID_POST_INIT_CallIn Call Prototype - * @par - * sbMidPostInit ((AMDSBCFG*)pConfig) (Followed PH Interface) - * @subsection SB_MID_POST_INIT_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_MID_POST_INIT --> 0x00010021 </TD></TR> - * </TABLE> - * @subsection SB_MID_POST_INIT_CallOut Prepare for Callout - * @par - * Not Applicable (Not necessary for the current implementation) - * @subsection SB_MID_POST_INIT_Config Prepare for Configuration Data. - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * </TABLE> - * - */ -#define SB_MID_POST_INIT 0x00010021 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_LATE_POST_INIT_Page SB_LATE_POST_INIT - * @section SB_LATE_POST_INIT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_LATE_POST_INIT_CallIn Call Prototype - * @par - * sbLatePost ((AMDSBCFG*)pConfig) (Followed PH Interface) - * @subsection SB_LATE_POST_INIT_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_LATE_POST_INIT --> 0x00010030 </TD></TR> - * </TABLE> - * @subsection SB_LATE_POST_INIT_CallOut Prepare for Callout - * @par - * Not Applicable (Not necessary for the current implementation) - * @subsection SB_LATE_POST_INIT_Config Prepare for Configuration Data. - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * </TABLE> - * - */ -#define SB_LATE_POST_INIT 0x00010030 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_BEFORE_PCI_RESTORE_INIT_Page SB_BEFORE_PCI_RESTORE_INIT - * @section SB_BEFORE_PCI_RESTORE_INIT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallIn Call Prototype - * @par - * sbBeforePciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface) - * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_RESTORE_INIT --> 0x00010040 </TD></TR> - * </TABLE> - * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallOut Prepare for Callout - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR> - * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR> - * </TABLE> - * @subsection SB_BEFORE_PCI_RESTORE_INIT_Config Prepare for Configuration Data. - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * </TABLE> - * - */ -#define SB_BEFORE_PCI_RESTORE_INIT 0x00010040 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_AFTER_PCI_RESTORE_INIT_Page SB_AFTER_PCI_RESTORE_INIT - * @section SB_AFTER_PCI_RESTORE_INIT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_AFTER_PCI_RESTORE_INIT_CallIn Call Prototype - * @par - * sbAfterPciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface) - * @subsection SB_AFTER_PCI_RESTORE_INIT_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_AFTER_PCI_RESTORE_INIT --> 0x00010050 </TD></TR> - * </TABLE> - * @subsection SB_AFTER_PCI_RESTORE_INIT_CallOut Prepare for Callout - * @par - * Not Applicable (Not necessary for the current implementation) - * @subsection SB_AFTER_PCI_RESTORE_INIT_Config Prepare for Configuration Data. - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR> - * </TABLE> - * - */ -#define SB_AFTER_PCI_RESTORE_INIT 0x00010050 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_SMM_SERVICE_Page SB_SMM_SERVICE - * @section SB_SMM_SERVICE Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_SMM_SERVICE_CallIn Call Prototype - * @par - * sbSmmService ((AMDSBCFG*)pConfig) (Followed PH Interface) - * @subsection SB_SMM_SERVICE_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_SMM_SERVICE --> 0x00010060 </TD></TR> - * </TABLE> - * @subsection SB_SMM_SERVICE_CallOut Prepare for Callout - * @par - * Not Applicable (Not necessary for the current implementation) - * @subsection SB_SMM_SERVICE_Config Prepare for Configuration Data. - * @par - * Not necessary on current implementation - * - */ -#define SB_SMM_SERVICE 0x00010060 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page SB_SMM_ACPION_Page SB_SMM_ACPION - * @section SB_SMM_ACPION Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection SB_SMM_ACPION_CallIn Call Prototype - * @par - * sbSmmAcpiOn ((AMDSBCFG*)pConfig) (Followed PH Interface) - * @subsection SB_SMM_ACPION_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> SB_SMM_ACPION --> 0x00010061 </TD></TR> - * </TABLE> - * @subsection SB_SMM_ACPION_CallOut Prepare for Callout - * @par - * Not Applicable (Not necessary for the current implementation) - * @subsection SB_SMM_ACPION_Config Prepare for Configuration Data. - * @par - * Not necessary on current implementation - * - */ -#define SB_SMM_ACPION 0x00010061 -#define SB_EC_FANCONTROL 0x00010070 - -#ifndef OEM_CALLBACK_BASE - #define OEM_CALLBACK_BASE 0x00010100 -#endif - -//0x00 - 0x0F callback functions are reserved for bootblock -#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 -#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT - * @section CB_SBGPP_RESET_ASSERT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR> - * </TABLE> - * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data. - * @par - * Not necessary on current implementation - * - */ -#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30 -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT - * @section CB_SBGPP_RESET_DEASSERT Interface Call - * Initialize structure referenced by AMDSBCFG to default recommended value. - * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID - * @par - * <TABLE border="0"> - * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR> - * </TABLE> - * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data. - * @par - * Not necessary on current implementation - * - */ -#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31 - -#define IMC_FIRMWARE_FAIL OEM_CALLBACK_BASE + 0x40 - -#define CFG_ADDR_PORT 0xCF8 -#define CFG_DATA_PORT 0xCFC - -#define ALINK_ACCESS_INDEX 0x0CD8 -#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 - -/*------------------------------------------------------------------ -; I/O Base Address - Should be set by host BIOS -;------------------------------------------------------------------ */ -#define DELAY_PORT 0x0E0 - -/*------------------------------------------------------------------ -; Fuse ID and minor ID of efuse bits -;------------------------------------------------------------------ */ -#define FUSE_ID_EFUSE_LOC 0x1F // efuse bits 248-255 -#define MINOR_ID_EFUSE_LOC 0x1E // efuse bits 240-247 -#define M1_D1_FUSE_ID 0x70 -#define M1_MINOR_ID 0x02 - -/*------------------------------------------------------------------ -; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display -;------------------------------------------------------------------ */ -// ASIC VendorID and DeviceIDs -#define AMD_SB_VID 0x1002 -#define SB_DEVICE_ID 0x4385 /* AMD ER SB800 */ -#define V_SB_SATA_VID AMD_SB_VID // dev 17 Func 0 -#define V_SB_SATA_DID 0x4390 -#define V_SB_SATA_AHCI_DID 0x4391 -#define V_SB_SATA_RAID_DID 0x4392 -#define V_SB_SATA_RAID5_DID 0x4393 -#define V_SB_USB_OHCI_VID AMD_SB_VID // dev 18 Func 0, dev 19 Func 0, dev 22 Func 0 -#define V_SB_USB_OHCI_DID 0x4397 -#define V_SB_USB_EHCI_VID AMD_SB_VID // dev 18 Func 2, dev 19 Func 2, dev 22 Func 2 -#define V_SB_USB_EHCI_DID 0x4396 -#define V_SB_SMBUS_VID AMD_SB_VID // dev 20 Func 0 -#define V_SB_SMBUS_DID 0x4385 -#define V_SB_IDE_VID AMD_SB_VID // dev 20 Func 1 -#define V_SB_IDE_DID 0x439C -#define V_SB_AZALIA_VID AMD_SB_VID // dev 20 Func 2 -#define V_SB_AZALIA_DID 0x4383 -#define V_SB_LPC_VID AMD_SB_VID // dev 20 Func 3 -#define V_SB_LPC_DID 0x439D -#define V_SB_PCIB_VID AMD_SB_VID // dev 20 Func 4 -#define V_SB_PCIB_DID 0x4384 -#define V_SB_USB_OHCIF_VID AMD_SB_VID // dev 20 Func 5 -#define V_SB_USB_OHCIF_DID 0x4399 -#define V_SB_NIC_VID 0x14E4 // dev 20 Func 6 -#define V_SB_NIC_DID 0x1699 - -//Misc -#define ACPI_SMI_CMD_PORT 0xB0 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define R_SB_PM_ACPI_PMA_CNT_BLK_LO 0x2C - -#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) -#define SB_SATA1_BUS 0 -#define SB_SATA1_DEV 17 -#define SB_SATA1_FUNC 0 - -#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) -#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4 -#define SB_OHCI1_BUS 0 -#define SB_OHCI1_DEV 18 -#define SB_OHCI1_FUNC 0 -#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9 -#define SB_OHCI2_BUS 0 -#define SB_OHCI2_DEV 19 -#define SB_OHCI2_FUNC 0 -#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13 -#define SB_OHCI3_BUS 0 -#define SB_OHCI3_DEV 22 -#define SB_OHCI3_FUNC 0 -#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4 -#define SB_EHCI1_BUS 0 -#define SB_EHCI1_DEV 18 -#define SB_EHCI1_FUNC 2 -#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9 -#define SB_EHCI2_BUS 0 -#define SB_EHCI2_DEV 19 -#define SB_EHCI2_FUNC 2 -#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13 -#define SB_EHCI3_BUS 0 -#define SB_EHCI3_DEV 22 -#define SB_EHCI3_FUNC 2 - -#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) -#define SB_ISA_BUS 0 -#define SB_ISA_DEV 20 -#define SB_ISA_FUNC 0 -#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) -#define SB_IDE_BUS 0 -#define SB_IDE_DEV 20 -#define SB_IDE_FUNC 1 -#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2) -#define SB_AZALIA_BUS 0 -#define SB_AZALIA_DEV 20 -#define SB_AZALIA_FUNC 2 -#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) -#define SB_LPC_BUS 0 -#define SB_LPC_DEV 20 -#define SB_LPC_FUNC 3 -#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700 -#define SB_PCI_BUS 0 -#define SB_PCI_DEV 20 -#define SB_PCI_FUNC 4 -#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1 -#define SB_OHCI4_BUS 0 -#define SB_OHCI4_DEV 20 -#define SB_OHCI4_FUNC 5 -//Gigabyte Ethernet Controller -#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6) -#define SB_GBEC_BUS 0 -#define SB_GBEC_DEV 20 -#define SB_GBEC_FUNC 6 - -#define SB_GPP_BUS 0 -#define SB_GPP_DEV 21 -#define SB_GPP_FUNC 0 -#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0 -#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1 -#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2 -#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3 - -#define ACPI_MMIO_BASE 0xFED80000 -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 - -#define GPP_EFUSE_LOCATION 0x14 // bit 160 -#define GPP_GEN2_EFUSE_BIT BIT0 - -// RegSpace field (AB_INDEX[31:29] -#define AXINDC 0 // AXINDC -#define AXINDP 2 // AXINDP -#define ABCFG 6 // ABCFG -#define AXCFG 4 // AXCFG -#define RCINDXC 1 // PCIEIND -#define RCINDXP 3 // PCIEIND_P - -#define SBTEMP_BUS 8 -#define GPP_DEV_NUM 21 //?? Code style different -#define MAX_GPP_PORTS 4 -#ifndef TRUE - #define TRUE 1 -#endif -#ifndef FALSE - #define FALSE 0 -#endif -// -// ABCFG Registers -// -#define SB_ABCFG_REG00 0x00 // VENDOR ID -#define SB_ABCFG_REG08 0x08 // REVISION ID -#define SB_ABCFG_REG40 0x40 // BL_EVENTCNT0LO -#define SB_ABCFG_REG44 0x44 // BL_EVENTCNT1LO -#define SB_ABCFG_REG48 0x48 // BL_EVENTCNTSEL -#define SB_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI -#define SB_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI -#define SB_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL -#define SB_ABCFG_REG50 0x50 // MISCCTL_50 -#define SB_ABCFG_REG54 0x54 // MISCCTL_54 -#define SB_ABCFG_REG58 0x58 // BL RAB CONTROL - -#define SB_ABCFG_REG60 0x60 // LINKWIDTH_CTL -#define SB_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL -#define SB_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL -#define SB_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS -#define SB_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS -#define SB_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE -#define SB_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE - -#define SB_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL -#define SB_ABCFG_REG88 0x88 // -#define SB_ABCFG_REG90 0x90 // BIF CONTROL 0 -#define SB_ABCFG_REG94 0x94 // MSI CONTROL -#define SB_ABCFG_REG98 0x98 // BIF CONTROL 1 -#define SB_ABCFG_REG9C 0x9C // MISCCTL_9C -#define SB_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE -#define SB_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4 -#define SB_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8 -#define SB_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING -#define SB_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE -#define SB_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP -#define SB_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA -#define SB_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL -#define SB_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA -#define SB_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS -#define SB_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL -#define SB_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL -#define SB_ABCFG_REGFC 0xFC // SB_TRAP_CONTROL -#define SB_ABCFG_REG100 0x100 // SB_TRAP0_ADDRL -#define SB_ABCFG_REG104 0x104 // SB_TRAP0_ADDRH -#define SB_ABCFG_REG108 0x108 // SB_TRAP0_CMD -#define SB_ABCFG_REG10C 0x10C // SB_TRAP1_DATA -#define SB_ABCFG_REG110 0x110 // SB_TRAP1_ADDRL -#define SB_ABCFG_REG114 0x114 // SB_TRAP1_ADDRH -#define SB_ABCFG_REG118 0x118 // SB_TRAP1_CMD -#define SB_ABCFG_REG11C 0x11C // SB_TRAP1_DATA -#define SB_ABCFG_REG120 0x120 // SB_TRAP2_ADDRL -#define SB_ABCFG_REG124 0x124 // SB_TRAP2_ADDRH -#define SB_ABCFG_REG128 0x128 // SB_TRAP2_CMD -#define SB_ABCFG_REG12C 0x12C // SB_TRAP2_DATA -#define SB_ABCFG_REG130 0x130 // SB_TRAP3_ADDRL -#define SB_ABCFG_REG134 0x134 // SB_TRAP3_ADDRH -#define SB_ABCFG_REG138 0x138 // SB_TRAP3_CMD -#define SB_ABCFG_REG13C 0x13C // SB_TRAP3_DATA -#define SB_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL -#define SB_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0 -#define SB_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1 -#define SB_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0 -#define SB_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A -#define SB_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B -#define SB_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C -#define SB_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D -#define SB_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0 -#define SB_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1 -#define SB_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2 -#define SB_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A -#define SB_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B -#define SB_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C -#define SB_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D -#define SB_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0 -#define SB_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1 -#define SB_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND -#define SB_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER -#define SB_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE -#define SB_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE -#define SB_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE -#define SB_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER -#define SB_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER -#define SB_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER -#define SB_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL -#define SB_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND -#define SB_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER -#define SB_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE -#define SB_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE -#define SB_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE -#define SB_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER -#define SB_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER -#define SB_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER -#define SB_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL -#define SB_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND -#define SB_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER -#define SB_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE -#define SB_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE -#define SB_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE -#define SB_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER -#define SB_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER -#define SB_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER -#define SB_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL -#define SB_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND -#define SB_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER -#define SB_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE -#define SB_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE -#define SB_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE -#define SB_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER -#define SB_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER -#define SB_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER -#define SB_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL -#define SB_ABCFG_REG10040 0x10040 // AL_EVENTCNT0LO -#define SB_ABCFG_REG10044 0x10044 // AL_EVENTCNT1LO -#define SB_ABCFG_REG10048 0x10048 // AL_EVENTCNTSEL -#define SB_ABCFG_REG1004A 0x1004A // AL_EVENTCNT0HI -#define SB_ABCFG_REG1004B 0x1004B // AL_EVENTCNT1HI -#define SB_ABCFG_REG1004C 0x1004C // AL_EVENTCNTCTL -#define SB_ABCFG_REG10050 0x10050 // MISCCTL_10050 -#define SB_ABCFG_REG10054 0x10054 // AL_ARB_CTL -#define SB_ABCFG_REG10056 0x10056 // AL_CLK_CTL -#define SB_ABCFG_REG10058 0x10058 // AL RAB CONTROL -#define SB_ABCFG_REG1005C 0x1005C // AL MLT CONTROL -#define SB_ABCFG_REG10060 0x10060 // AL DMA PREFETCH ENABLE -#define SB_ABCFG_REG10064 0x10064 // AL DMA PREFETCH FLUSH CONTROL -#define SB_ABCFG_REG10068 0x10068 // AL PREFETCH LIMIT -#define SB_ABCFG_REG1006C 0x1006C // AL DMA PREFETCH CONTROL -#define SB_ABCFG_REG10070 0x10070 // MISCCTL_10070 -#define SB_ABCFG_REG10080 0x10080 // CLKMUXSTATUS -#define SB_ABCFG_REG10090 0x10090 // BIF CONTROL 0 -#define SB_ABCFG_REG1009C 0x1009C // MISCCTL_1009C - -// -// RCINDX_P Registers -// -#define SB_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH -#define SB_RCINDXP_REG10 0x10 | RCINDXP << 29 // -#define SB_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL -#define SB_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS -#define SB_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL -#define SB_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL -#define SB_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL -#define SB_RCINDXP_REGA2 0xA2 | RCINDXP << 29 // -#define SB_RCINDXP_REGA4 0xA4 | RCINDXP << 29 // -#define SB_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0 -#define SB_RCINDXP_REGC0 0xC0 | RCINDXP << 29 // - -// -// RCINDX_C Registers -// -#define SB_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG -#define SB_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL -#define SB_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // - -// -// AXINDC Registers -// -#define SB_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG -#define SB_AX_INDXC_REG10 0x10 -#define SB_AX_INDXC_REG30 0x30 -#define SB_AX_DATAC_REG34 0x34 -#define SB_AX_INDXP_REG38 0x38 -#define SB_AX_DATAP_REG3C 0x3C -#define SB_AX_INDXC_REG40 0x40 | AXINDC << 29 -#define SB_AX_INDXC_REGA4 0xA4 | AXINDC << 29 - -#define SB_AX_INDXP_REGA0 0xA0 | AXINDP << 29 -#define SB_AX_INDXP_REGA4 0xA4 | AXINDP << 29 -#define SB_AX_INDXP_REGB1 0xB1 | AXINDP << 29 - -#define SB_AX_CFG_REG88 0x88 | AXCFG << 29 - -#define AX_INDXC 0 -#define AX_INDXP 1 -#define SB_AB_REG04 0x04 -#define SB_AB_REG40 0x40 - -#define RC_INDXC_REG40 0x40 | RCINDXC << 29 -#define RC_INDXC_REG65 0x65 | RCINDXC << 29 - -// -// SATA Device 0x4390 (IDE) -// 0x4391 (AHCI) -// 0x4392 (AHCI/RAID Promise with RAID driver) -// 0x4393 (RAID5) -// 0x4394/0x4395 (SATA HyperFlash OneNand support/SATA HyperFlash-PCIe support) -// Device 17 (0x11) Func 0 -// -//Sata Controller Mode -#define NATIVE_IDE_MODE 0 -#define RAID_MODE 1 -#define AHCI_MODE 2 -#define LEGACY_IDE_MODE 3 -#define IDE_TO_AHCI_MODE 4 -#define AHCI_MODE_4394 5 -#define IDE_TO_AHCI_MODE_4394 6 - -//Sata Port Configuration -#define SIX_PORTS 0 -#define FOUR_PORTS 1 - -#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133 -#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169 -#define SATA_EFUSE_BIT 0x20 // -#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits -#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits -#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits -#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits -#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08 -#define SB_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits -#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits -#define SB_SATA_REG0E 0x00E // Header Type - R - 8 bits -#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits -#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits -#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits -#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits -#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits -#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits -#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits -#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits -#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits -#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits -#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits -#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits -#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits -#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits -#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits -#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits -#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits -#define SB_SATA_REG48 0x048 -#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits -#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits -#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits -#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits -#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits -#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits -#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits -#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits -#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits -#define SB_SATA_REG68 0x068 // MSI Program - R/W - 8 bits -#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits -#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits -#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits -#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits -#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits -#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits -#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits -#define SB_SATA_REG86 0x086 // PY Global Control -#define SB_SATA_REG87 0x087 -#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23) -#define SB_SATA_REG8A 0x08A -#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23) -#define SB_SATA_REG8E 0x08E -#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23) -#define SB_SATA_REG92 0x092 -#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23) -#define SB_SATA_REG96 0x096 -#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits -#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits -#define SB_SATA_REGA0 0x0A0 // -#define SB_SATA_REGA4 0x0A4 // -#define SB_SATA_REGA5 0x0A5 //; -#define SB_SATA_REGA8 0x0A8 // -#define SB_SATA_REGAD 0x0AD //; -#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits -#define SB_SATA_REGB5 0x0B5 //; -#define SB_SATA_REGBD 0x0BD //; -#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits -#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits - -#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits -#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits -#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits -#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits -#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits -#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits -#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits -#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits -#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits -#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits -#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits -#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits -#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits -#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits -#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits -#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits -#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits -#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits -#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits -#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits -#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits -#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits -#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits -#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits -#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits -#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits -#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits -#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits -#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration -#define SB_SATA_BAR5_REGFC 0x0FC -#define SB_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 -#define SB_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel -#define SB_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel -#define SB_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel -#define SB_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits -#define SB_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)] -#define SB_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)] -#define SB_SATA_BAR5_REG120 0x0120 // -#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status -#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control -#define SB_SATA_BAR5_REG130 0x0130 -#define SB_SATA_BAR5_REG1B0 0x01B0 -#define SB_SATA_BAR5_REG230 0x0230 -#define SB_SATA_BAR5_REG2B0 0x02B0 -#define SB_SATA_BAR5_REG330 0x0330 -#define SB_SATA_BAR5_REG3B0 0x03B0 - -// -// FC Device 0x439B -// Device 17 (0x11) Func 1 -// -#define SB_FC_REG00 0x00 // Device/Vendor ID - R -#define SB_FC_REG04 0x04 // Command - RW -#define SB_FC_REG10 0x10 // BAR - -#define SB_FC_MMIO_REG70 0x070 -#define SB_FC_MMIO_REG200 0x200 - -// -// USB OHCI Device 0x4397 -// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0 -// Device 20 (0x14) Func 5 (FL) -// -#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002) -#define SB_OHCI_REG04 0x04 // Command - RW -#define SB_OHCI_REG06 0x06 // Status - R -#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R -#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW -#define SB_OHCI_REG10 0x10 // Bar_OCI - RW -#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW -#define SB_OHCI_REG34 0x34 // Capability Pointer - R -#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW -#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW -#define SB_OHCI_REG40 0x40 // Config Timers - RW -#define SB_OHCI_REG42 0x42 // Port Disable Control - RW (800) -#define SB_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800) -#define SB_OHCI_REG48 0x48 // Port Force Reset - RW (800) -#define SB_OHCI_REG4C 0x4C // MSI - RW (800) -#define SB_OHCI_REG50 0x50 // Misc Control - RW -#define SB_OHCI_REG51 0x51 -#define SB_OHCI_REG52 0x52 -#define SB_OHCI_REG58 0x58 // Over Current Control - RW -#define SB_OHCI_REG5C 0x5C // Over Current Control - RW (800)?? -#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R (800)?? -#define SB_OHCI_REG68 0x68 // Over Current PME Enable - RW -#define SB_OHCI_REG74 0x74 // Target Timeout Control - RW (800) -#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW -#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW -#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW -#define SB_OHCI_REGE4 0x0E4 // HT MSI Support -#define SB_OHCI_REGF0 0x0F0 // Function Level Reset Capability -#define SB_OHCI_REGF4 0x0F4 // Function Level Reset Control - -#define SB_OHCI_BAR_REG00 0x00 // cRevision - R -#define SB_OHCI_BAR_REG04 0x04 // cControl -#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus -#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW -#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable -#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable -#define SB_OHCI_BAR_REG18 0x18 // HcCCA -#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED -#define SB_OHCI_BAR_REG20 0x20 // HcControleadED -#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW -#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED -#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW -#define SB_OHCI_BAR_REG30 0x30 // HcDoneead -#define SB_OHCI_BAR_REG34 0x34 // cFmInterval -#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining -#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber -#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart -#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold -#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA -#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB -#define SB_OHCI_BAR_REG50 0x50 // HcRStatus -#define SB_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800) -#define SB_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800) -#define SB_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800) - -// -// USB EHCI Device 0x4396 -// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2 -// -#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R -#define SB_EHCI_REG04 0x04 // Command - RW -#define SB_EHCI_REG06 0x06 // Status - R -#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R -#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW -#define SB_EHCI_REG10 0x10 // BAR - RW -#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW -#define SB_EHCI_REG34 0x34 // Capability Pointer - R -#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW -#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW ?? -#define SB_EHCI_REG40 0x40 // Config Timers - RW ?? -#define SB_EHCI_REG4C 0x4C // MSI - RW -#define SB_EHCI_REG50 0x50 // EHCI Misc Control - RW -#define SB_EHCI_REG54 0x54 // EHCI Misc Control - RW -#define SB_EHCI_REG60 0x60 // SBRN - R -#define SB_EHCI_REG61 0x61 // FLADJ - RW -#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW -#define SB_EHCI_REGC0 0x0C0 // PME control - RW (800) -#define SB_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800) -#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW -#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW -#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW -#define SB_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800) -#define SB_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800) -#define SB_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800) - -#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R -#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R -#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R -#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R -#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R - -#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits -#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits -#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits -#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits -#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits -#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits -#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits -#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits -#define SB_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits -#define SB_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800) -#define SB_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits -#define SB_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R -#define SB_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R -#define SB_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R -#define SB_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800) -#define SB_EHCI_BAR_REGB8 0x0B8 // Loopback Test -#define SB_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control -#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration -#define SB_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control -#define SB_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose -#define SB_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) ** -#define SB_EHCI_BAR_REG100 0x100 // USB debug port - -// -// SB800 SB CFG device 0x4385 -// Device 20 (0x14) Func 0 -// -#define SB_CFG_REG00 0x000 // VendorID - R -#define SB_CFG_REG02 0x002 // DeviceID - R -#define SB_CFG_REG04 0x004 // Command- RW -#define SB_CFG_REG05 0x005 // Command- RW -#define SB_CFG_REG06 0x006 // STATUS- RW -#define SB_CFG_REG08 0x008 // Revision ID/Class Code- R -#define SB_CFG_REG0A 0x00A // -#define SB_CFG_REG0B 0x00B // -#define SB_CFG_REG0C 0x00C // Cache Line Size- R -#define SB_CFG_REG0D 0x00D // Latency Timer- R -#define SB_CFG_REG0E 0x00E // Header Type- R -#define SB_CFG_REG0F 0x00F // BIST- R -#define SB_CFG_REG10 0x010 // Base Address 0- R -#define SB_CFG_REG11 0x011 //; -#define SB_CFG_REG12 0x012 //; -#define SB_CFG_REG13 0x013 //; -#define SB_CFG_REG14 0x014 // Base Address 1- R -#define SB_CFG_REG18 0x018 // Base Address 2- R -#define SB_CFG_REG1C 0x01C // Base Address 3- R -#define SB_CFG_REG20 0x020 // Base Address 4- R -#define SB_CFG_REG24 0x024 // Base Address 5- R -#define SB_CFG_REG28 0x028 // Cardbus CIS Pointer- R -#define SB_CFG_REG2C 0x02C // Subsystem Vendor ID- W -#define SB_CFG_REG2E 0x02E // Subsystem ID- W -#define SB_CFG_REG30 0x030 // Expansion ROM Base Address - R -#define SB_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00 -#define SB_CFG_REG3C 0x03C // Interrupt Line - R -#define SB_CFG_REG3D 0x03D // Interrupt Pin - R -#define SB_CFG_REG3E 0x03E // Min_Gnt - R -#define SB_CFG_REG3F 0x03F // Max_Lat - R -#define SB_CFG_REG90 0x090 // Smbus Base Address - R -#define SB_CFG_REG9C 0x09C // SBResourceMMIO_BASE - -// -// SB800 SATA IDE device 0x439C -// Device 20 (0x14) Func 1 -// - -#define SB_IDE_REG00 0x00 // Vendor ID -#define SB_IDE_REG02 0x02 // Device ID -#define SB_IDE_REG04 0x04 // Command -#define SB_IDE_REG06 0x06 // Status -#define SB_IDE_REG08 0x08 // Revision ID/Class Code -#define SB_IDE_REG09 0x09 // Class Code -#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID -#define SB_IDE_REG34 0x34 -#define SB_IDE_REG40 0x40 // Configuration - RW - 32 bits -#define SB_IDE_REG62 0x62 // IDE Internal Control -#define SB_IDE_REG63 0x63 // IDE Internal Control -// -// SB800 AZALIA device 0x4383 -// Device 20 (0x14) Func 2 -// -#define ATI_AZALIA_ExtBlk_Addr 0x0F8 -#define ATI_AZALIA_ExtBlk_DATA 0x0FC - -#define SB_AZ_REG00 0x00 // Vendor ID - R -#define SB_AZ_REG02 0x02 // Device ID - R/W -#define SB_AZ_REG04 0x04 // PCI Command -#define SB_AZ_REG06 0x06 // PCI Status - R/W -#define SB_AZ_REG08 0x08 // Revision ID -#define SB_AZ_REG09 0x09 // Programming Interface -#define SB_AZ_REG0A 0x0A // Sub Class Code -#define SB_AZ_REG0B 0x0B // Base Class Code -#define SB_AZ_REG0C 0x0C // Cache Line Size - R/W -#define SB_AZ_REG0D 0x0D // Latency Timer -#define SB_AZ_REG0E 0x0E // Header Type -#define SB_AZ_REG0F 0x0F // BIST -#define SB_AZ_REG10 0x10 // Lower Base Address Register -#define SB_AZ_REG14 0x14 // Upper Base Address Register -#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID -#define SB_AZ_REG2D 0x2D // Subsystem ID -#define SB_AZ_REG34 0x34 // Capabilities Pointer -#define SB_AZ_REG3C 0x3C // Interrupt Line -#define SB_AZ_REG3D 0x3D // Interrupt Pin -#define SB_AZ_REG3E 0x3E // Minimum Grant -#define SB_AZ_REG3F 0x3F // Maximum Latency -#define SB_AZ_REG40 0x40 // Misc Control 1 -#define SB_AZ_REG42 0x42 // Misc Control 2 Register -#define SB_AZ_REG43 0x43 // Misc Control 3 Register -#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register -#define SB_AZ_REG46 0x46 // Debug Control Register -#define SB_AZ_REG4C 0x4C -#define SB_AZ_REG50 0x50 // Power Management Capability ID -#define SB_AZ_REG52 0x52 // Power Management Capabilities -#define SB_AZ_REG54 0x54 // Power Management Control/Status -#define SB_AZ_REG60 0x60 // MSI Capability ID -#define SB_AZ_REG62 0x62 // MSI Message Control -#define SB_AZ_REG64 0x64 // MSI Message Lower Address -#define SB_AZ_REG68 0x68 // MSI Message Upper Address -#define SB_AZ_REG6C 0x6C // MSI Message Data - -#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R -#define SB_AZ_BAR_REG02 0x02 // Minor Version - R -#define SB_AZ_BAR_REG03 0x03 // Major Version - R -#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R -#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R -#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W -#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W -#define SB_AZ_BAR_REG0E 0x0E // State Change Status - R/W -#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W -#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R -#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R -#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W -#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W -#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R -#define SB_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W -#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W -#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW -#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W -#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W -#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W -#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W -#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W -#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW -#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW -#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW -#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W -#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W -#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W -#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W -#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W -#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W -#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W -#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W -#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W -#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R - -// -// SB800 LPC Device 0x439D -// Device 20 (0x14) Func 3 -// -#define SB_LPC_REG00 0x00 // VID- R -#define SB_LPC_REG02 0x02 // DID- R -#define SB_LPC_REG04 0x04 // CMD- RW -#define SB_LPC_REG06 0x06 // STATUS- RW -#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R -#define SB_LPC_REG0C 0x0C // Cache Line Size - R -#define SB_LPC_REG0D 0x0D // Latency Timer - R -#define SB_LPC_REG0E 0x0E // Header Type - R -#define SB_LPC_REG0F 0x0F // BIST- R -#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW* -#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro -#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro -#define SB_LPC_REG40 0x40 // PCI Control - RW -#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW -#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW -#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW -#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW -#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW -#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW -#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW -#define SB_LPC_REG4C 0x4C // Memory Range Register - RW -#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW -#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW -#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW -#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW -#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - -#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - -#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW -#define SB_LPC_REG65 0x65 -#define SB_LPC_REG66 0x66 -#define SB_LPC_REG67 0x67 -#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW -#define SB_LPC_REG69 0x69 -#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW -#define SB_LPC_REG6B 0x6B -#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW -#define SB_LPC_REG6D 0x6D -#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW -#define SB_LPC_REG6F 0x6F -#define SB_LPC_REG70 0x70 // Firmware ub Select - RW* -#define SB_LPC_REG71 0x71 -#define SB_LPC_REG72 0x72 -#define SB_LPC_REG73 0x73 -#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R -#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R -#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R -#define SB_LPC_REG9C 0x9C -#define SB_LPC_REG80 0x80 // MSI Capability Register- R -#define SB_LPC_REGA0 0x0A0 // SPI base address -#define SB_LPC_REGA1 0x0A1 // SPI base address -#define SB_LPC_REGA2 0x0A2 // SPI base address -#define SB_LPC_REGA3 0x0A3 // SPI base address -#define SB_LPC_REGA4 0x0A4 -#define SB_LPC_REGBA 0x0BA // EcControl -#define SB_LPC_REGBB 0x0BB // HostControl - -// -// SB800 PCIB 0x4384 -// Device 20 (0x14) Func 4 -// -#define SB_PCIB_REG04 0x04 // Command -#define SB_PCIB_REG0D 0x0D // Primary Master Latency Timer -#define SB_PCIB_REG1B 0x1B // Secondary Latency Timer -#define SB_PCIB_REG1C 0x1C // IO Base -#define SB_PCIB_REG1D 0x1D // IO Limit -#define SB_PCIB_REG40 0x40 // CPCTRL -#define SB_PCIB_REG42 0x42 // CLKCTRL -#define SB_PCIB_REG48 0x48 // -#define SB_PCIB_REG4A 0x4A // PCICLK Enable Bits -#define SB_PCIB_REG4B 0x4B // Misc Control -#define SB_PCIB_REG4C 0x4C // AutoClockRun Control -#define SB_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override -#define SB_PCIB_REG65 0x65 // Misc Control -#define SB_PCIB_REG66 0x66 // Misc Control -// -// SB800 NIC 0x4384 -// Device 20 (0x14) Func 6 (Func5 OHCI FL device) -// -#define SB_GEC_REG04 0x04 // Command -#define SB_GEC_REG10 0x10 // GEC BAR - -// -// SB800 SB MMIO Base (SMI) -// offset : 0x200 -// -#define SB_SMI_REG00 0x00 // EventStatus -#define SB_SMI_REG04 0x04 // EventEnable -#define SB_SMI_REG08 0x08 // SciTrig -#define SB_SMI_REG0C 0x0C // SciLevl -#define SB_SMI_REG10 0x10 // SmiSciStatus -#define SB_SMI_REG14 0x14 // SmiSciEn -#define SB_SMI_REG18 0x18 // ForceSciEn -#define SB_SMI_REG1C 0x1C // SciRwData -#define SB_SMI_REG20 0x20 // SciS0En -#define SB_SMI_Gevent0 0x40 // SciMap0 -#define SB_SMI_Gevent1 0x41 // SciMap1 -#define SB_SMI_Gevent2 0x42 // SciMap2 -#define SB_SMI_Gevent3 0x43 // SciMap3 -#define SB_SMI_Gevent4 0x44 // SciMap4 -#define SB_SMI_Gevent5 0x45 // SciMap5 -#define SB_SMI_Gevent6 0x46 // SciMap6 -#define SB_SMI_Gevent7 0x47 // SciMap7 -#define SB_SMI_Gevent8 0x48 // SciMap8 -#define SB_SMI_Gevent9 0x49 // SciMap9 -#define SB_SMI_Gevent10 0x4A // SciMap10 -#define SB_SMI_Gevent11 0x4B // SciMap11 -#define SB_SMI_Gevent12 0x4C // SciMap12 -#define SB_SMI_Gevent13 0x4D // SciMap13 -#define SB_SMI_Gevent14 0x4E // SciMap14 -#define SB_SMI_Gevent15 0x4F // SciMap15 -#define SB_SMI_Gevent16 0x50 // SciMap16 -#define SB_SMI_Gevent17 0x51 // SciMap17 -#define SB_SMI_Gevent18 0x52 // SciMap18 -#define SB_SMI_Gevent19 0x53 // SciMap19 -#define SB_SMI_Gevent20 0x54 // SciMap20 -#define SB_SMI_Gevent21 0x55 // SciMap21 -#define SB_SMI_Gevent22 0x56 // SciMap22 -#define SB_SMI_Gevent23 0x57 // SciMap23 -#define SB_SMI_Usbwakup0 0x58 // SciMap24 -#define SB_SMI_Usbwakup1 0x59 // SciMap25 -#define SB_SMI_Usbwakup2 0x5A // SciMap26 -#define SB_SMI_Usbwakup3 0x5B // SciMap27 -#define SB_SMI_SBGppPme0 0x5C // SciMap28 -#define SB_SMI_SBGppPme1 0x5D // SciMap29 -#define SB_SMI_SBGppPme2 0x5E // SciMap30 -#define SB_SMI_SBGppPme3 0x5F // SciMap31 -#define SB_SMI_SBGppHp0 0x60 // SciMap32 -#define SB_SMI_SBGppHp1 0x61 // SciMap33 -#define SB_SMI_SBGppHp2 0x62 // SciMap34 -#define SB_SMI_SBGppHp3 0x63 // SciMap35 -#define SB_SMI_AzaliaPme 0x64 // SciMap36 -#define SB_SMI_SataGevent0 0x65 // SciMap37 -#define SB_SMI_SataGevent1 0x66 // SciMap38 -#define SB_SMI_GecPme 0x67 // SciMap39 -#define SB_SMI_IMCGevent0 0x68 // SciMap40 -#define SB_SMI_IMCGevent1 0x69 // SciMap41 -#define SB_SMI_CIRPme 0x6A // SciMap42 -#define SB_SMI_WakePinGevent 0x6B // SciMap43 -#define SB_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent -#define SB_SMI_ASFMasterIntr 0x6D // SciMap45 -#define SB_SMI_ASFSlaveIntr 0x6E // SciMap46 -#define SB_SMI_SMBUS0 0x6F // SciMap47 -#define SB_SMI_TWARN 0x70 // SciMap48 -#define SB_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr - -// Empty from 0x72-0x7F -//#Define SB_SMI_REG7C 0x7F // SciMap63 *** - -#define SB_SMI_REG80 0x80 // SmiStatus0 -#define SB_SMI_REG84 0x84 // SmiStatus1 -#define SB_SMI_REG88 0x88 // SmiStatus2 -#define SB_SMI_REG8C 0x8C // SmiStatus3 -#define SB_SMI_REG90 0x90 // SmiStatus4 -#define SB_SMI_REG94 0x94 // SmiPointer -#define SB_SMI_REG96 0x96 // SmiTimer -#define SB_SMI_REG98 0x98 // SmiTrig -#define SB_SMI_REG9C 0x9C // SmiTrig -#define SB_SMI_REGA0 0xA0 -#define SB_SMI_REGA1 0xA1 -#define SB_SMI_REGA2 0xA2 -#define SB_SMI_REGA3 0xA3 -#define SB_SMI_REGA4 0xA4 -#define SB_SMI_REGA5 0xA5 -#define SB_SMI_REGA6 0xA6 -#define SB_SMI_REGA7 0xA7 -#define SB_SMI_REGA8 0xA8 -#define SB_SMI_REGA9 0xA9 -#define SB_SMI_REGAA 0xAA -#define SB_SMI_REGAB 0xAB -#define SB_SMI_REGAC 0xAC -#define SB_SMI_REGAD 0xAD -#define SB_SMI_REGAE 0xAE -#define SB_SMI_REGAF 0xAF -#define SB_SMI_REGB0 0xB0 -#define SB_SMI_REGB1 0xB1 -#define SB_SMI_REGB2 0xB2 -#define SB_SMI_REGB3 0xB3 -#define SB_SMI_REGB4 0xB4 -#define SB_SMI_REGB5 0xB5 -#define SB_SMI_REGB6 0xB6 -#define SB_SMI_REGB7 0xB7 -#define SB_SMI_REGB8 0xB8 -#define SB_SMI_REGB9 0xB9 -#define SB_SMI_REGBA 0xBA -#define SB_SMI_REGBB 0xBB -#define SB_SMI_REGBC 0xBC -#define SB_SMI_REGBD 0xBD -#define SB_SMI_REGBE 0xBE -#define SB_SMI_REGBF 0xBF -#define SB_SMI_REGC0 0xC0 -#define SB_SMI_REGC1 0xC1 -#define SB_SMI_REGC2 0xC2 -#define SB_SMI_REGC3 0xC3 -#define SB_SMI_REGC4 0xC4 -#define SB_SMI_REGC5 0xC5 -#define SB_SMI_REGC6 0xC6 -#define SB_SMI_REGC7 0xC7 -#define SB_SMI_REGC8 0xC8 -#define SB_SMI_REGCA 0xCA // IoTrapping1 -#define SB_SMI_REGCC 0xCC // IoTrapping2 -#define SB_SMI_REGCE 0xCE // IoTrapping3 -#define SB_SMI_REGD0 0xD0 // MemTrapping0 -#define SB_SMI_REGD4 0xD4 // MemRdOvrData0 -#define SB_SMI_REGD8 0xD8 // MemTrapping1 -#define SB_SMI_REGDC 0xDC // MemRdOvrData1 -#define SB_SMI_REGE0 0xE0 // MemTrapping2 -#define SB_SMI_REGE4 0xE4 // MemRdOvrData2 -#define SB_SMI_REGE8 0xE8 // MemTrapping3 -#define SB_SMI_REGEC 0xEC // MemRdOvrData3 -#define SB_SMI_REGF0 0xF0 // CfgTrapping0 -#define SB_SMI_REGF4 0xF4 // CfgTrapping1 -#define SB_SMI_REGF8 0xF8 // CfgTrapping2 -#define SB_SMI_REGFC 0xFC // CfgTrapping3 - -// -// SB800 SB MMIO Base (PMIO) -// offset : 0x300 -// -#define SB_PMIOA_REG00 0x00 // ISA Decode -#define SB_PMIOA_REG04 0x04 // ISA Control -#define SB_PMIOA_REG08 0x08 // PCI Control -#define SB_PMIOA_REG0C 0x0C // StpClkSmaf -#define SB_PMIOA_REG10 0x10 // RetryDetect -#define SB_PMIOA_REG14 0x14 // StuckDetect -#define SB_PMIOA_REG20 0x20 // BiosRamEn -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn -#define SB_PMIOA_REG28 0x28 // AsfEn -#define SB_PMIOA_REG2C 0x2C // Smbus0En -#define SB_PMIOA_REG34 0x34 // IoApicEn -#define SB_PMIOA_REG3C 0x3C // SmartVoltEn -#define SB_PMIOA_REG40 0x40 // SmartVolt2En -#define SB_PMIOA_REG44 0x44 // BootTimerEn -#define SB_PMIOA_REG48 0x48 // WatchDogTimerEn -#define SB_PMIOA_REG4C 0x4C // WatchDogTimerConfig -#define SB_PMIOA_REG50 0x50 // HPETEn -#define SB_PMIOA_REG54 0x54 // SerialIrqConfig -#define SB_PMIOA_REG56 0x56 // RtcControl -#define SB_PMIOA_REG58 0x58 // VRT_T1 -#define SB_PMIOA_REG59 0x59 // VRT_T2 -#define SB_PMIOA_REG5A 0x5A // IntruderControl -#define SB_PMIOA_REG5B 0x5B // RtcShadow -#define SB_PMIOA_REG5C 0x5C -#define SB_PMIOA_REG5D 0x5D -#define SB_PMIOA_REG5E 0x5E // RtcExtIndex -#define SB_PMIOA_REG5F 0x5F // RtcExtData -#define SB_PMIOA_REG60 0x60 // AcpiPm1EvtBlk -#define SB_PMIOA_REG62 0x62 // AcpiPm1CntBlk -#define SB_PMIOA_REG64 0x64 // AcpiPmTmrBlk -#define SB_PMIOA_REG66 0x66 // P_CNTBlk -#define SB_PMIOA_REG68 0x68 // AcpiGpe0Blk -#define SB_PMIOA_REG6A 0x6A // AcpiSmiCmd -#define SB_PMIOA_REG6C 0x6C // AcpiPm2CntBlk -#define SB_PMIOA_REG6E 0x6E // AcpiPmaCntBlk -#define SB_PMIOA_REG74 0x74 // AcpiConfig -#define SB_PMIOA_REG78 0x78 // WakeIoAddr -#define SB_PMIOA_REG7A 0x7A // HaltCountEn -#define SB_PMIOA_REG7C 0x7C // C1eWrPortAdr -#define SB_PMIOA_REG7E 0x7E // CStateEn -#define SB_PMIOA_REG80 0x80 // BreakEvent -#define SB_PMIOA_REG84 0x84 // AutoArbEn -#define SB_PMIOA_REG88 0x88 // CStateControl -#define SB_PMIOA_REG8C 0x8C // StpClkHoldTime -#define SB_PMIOA_REG8E 0x8E // PopUpEndTime -#define SB_PMIOA_REG90 0x90 // C4Control -#define SB_PMIOA_REG94 0x94 // CStateTiming0 -#define SB_PMIOA_REG98 0x98 // CStateTiming1 -#define SB_PMIOA_REG9C 0x9C // C2Count -#define SB_PMIOA_REG9D 0x9D // C3Count -#define SB_PMIOA_REG9E 0x9E // C4Count -#define SB_PMIOA_REGA0 0xA0 // MessageCState -#define SB_PMIOA_REGA4 0xA4 // -#define SB_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime -#define SB_PMIOA_REGAA 0xAA // TrafficMonitorIntTime -#define SB_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount -#define SB_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount -#define SB_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick -#define SB_PMIOA_REGB4 0xB4 // FidVidControl -#define SB_PMIOA_REGB6 0xB6 // TPRESET1 -#define SB_PMIOA_REGB7 0xB7 // Tpreset1b -#define SB_PMIOA_REGB8 0xB8 // TPRESET2 -#define SB_PMIOA_REGB9 0xB9 // Test0 -#define SB_PMIOA_REGBA 0xBA // S_StateControl -#define SB_PMIOA_REGBC 0xBC // ThrottlingControl -#define SB_PMIOA_REGBE 0xBE // ResetControl -#define SB_PMIOA_REGBF 0xBF // ResetControl -#define SB_PMIOA_REGC0 0xC0 // S5Status -#define SB_PMIOA_REGC2 0xC2 // ResetStatus -#define SB_PMIOA_REGC4 0xC4 // ResetCommand -#define SB_PMIOA_REGC5 0xC5 // CF9Shadow -#define SB_PMIOA_REGC6 0xC6 // HTControl -#define SB_PMIOA_REGC8 0xC8 // Misc -#define SB_PMIOA_REGCC 0xCC // IoDrvSth -#define SB_PMIOA_REGD0 0xD0 // CLKRunEn -#define SB_PMIOA_REGD2 0xD2 // PmioDebug -#define SB_PMIOA_REGD6 0xD6 // IMCGating -#define SB_PMIOA_REGD8 0xD8 // MiscIndex -#define SB_PMIOA_REGD9 0xD9 // MiscData -#define SB_PMIOA_REGDA 0xDA // SataConfig -#define SB_PMIOA_REGDC 0xDC // HyperFlashConfig -#define SB_PMIOA_REGDE 0xDE // ABConfig -#define SB_PMIOA_REGE0 0xE0 // ABRegBar -#define SB_PMIOA_REGE6 0xE6 // FcEn -#define SB_PMIOA_REGEA 0xEA // PcibConfig -#define SB_PMIOA_REGEB 0xEB // AzEn -#define SB_PMIOA_REGEC 0xEC // LpcGating -#define SB_PMIOA_REGED 0xED // UsbGating -#define SB_PMIOA_REGEF 0xEF // UsbEnable -#define SB_PMIOA_REGF0 0xF0 // UsbControl -#define SB_PMIOA_REGF3 0xF3 // UsbDebug -#define SB_PMIOA_REGF6 0xF6 // GecEn -#define SB_PMIOA_REGF8 0xF8 // GecConfig -#define SB_PMIOA_REGFC 0xFC // TraceMemoryEn - -// -// SB800 SB MMIO Base (PMIO2) -// offset : 0x400 -// -#define SB_PMIO2_REG00 0x00 // Fan0InputControl -#define SB_PMIO2_REG01 0x01 // Fan0Control -#define SB_PMIO2_REG02 0x02 // Fan0Freq -#define SB_PMIO2_REG03 0x03 // LowDuty0 -#define SB_PMIO2_REG04 0x04 // MidDuty0 - -#define SB_PMIO2_REG10 0x00 // Fan1InputControl -#define SB_PMIO2_REG11 0x01 // Fan1Control -#define SB_PMIO2_REG12 0x02 // Fan1Freq -#define SB_PMIO2_REG13 0x03 // LowDuty1 -#define SB_PMIO2_REG14 0x04 // MidDuty1 - -#define SB_PMIO2_REG 0xFC // TraceMemoryEn - - -// -// SB800 SB MMIO Base (GPIO/IoMux) -// offset : 0x100/0xD00 -// -/* -GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226. -*/ -#define SB_GPIO_REG00 0x00 -#define SB_GPIO_REG32 0x20 -#define SB_GPIO_REG33 0x21 -#define SB_GPIO_REG34 0x22 -#define SB_GPIO_REG35 0x23 -#define SB_GPIO_REG36 0x24 -#define SB_GPIO_REG37 0x25 -#define SB_GPIO_REG38 0x26 -#define SB_GPIO_REG39 0x27 -#define SB_GPIO_REG40 0x28 -#define SB_GPIO_REG41 0x29 -#define SB_GPIO_REG42 0x2A -#define SB_GPIO_REG43 0x2B -#define SB_GPIO_REG44 0x2C -#define SB_GPIO_REG45 0x2D -#define SB_GPIO_REG46 0x2E -#define SB_GPIO_REG47 0x2F -#define SB_GPIO_REG48 0x30 -#define SB_GPIO_REG49 0x31 -#define SB_GPIO_REG50 0x32 -#define SB_GPIO_REG51 0x33 -#define SB_GPIO_REG52 0x34 -#define SB_GPIO_REG53 0x35 -#define SB_GPIO_REG54 0x36 -#define SB_GPIO_REG55 0x37 -#define SB_GPIO_REG56 0x38 -#define SB_GPIO_REG57 0x39 -#define SB_GPIO_REG58 0x3A -#define SB_GPIO_REG59 0x3B -#define SB_GPIO_REG60 0x3C -#define SB_GPIO_REG61 0x3D -#define SB_GPIO_REG62 0x3E -#define SB_GPIO_REG63 0x3F -#define SB_GPIO_REG64 0x40 -#define SB_GPIO_REG65 0x41 -#define SB_GPIO_REG66 0x42 -#define SB_GPIO_REG67 0x43 - -#define SB_GEVENT_REG00 0x60 -#define SB_GEVENT_REG01 0x61 -#define SB_GEVENT_REG02 0x62 -#define SB_GEVENT_REG03 0x63 -#define SB_GEVENT_REG04 0x64 -#define SB_GEVENT_REG05 0x65 -#define SB_GEVENT_REG06 0x66 -#define SB_GEVENT_REG07 0x67 -#define SB_GEVENT_REG08 0x68 -#define SB_GEVENT_REG09 0x69 -#define SB_GEVENT_REG10 0x6A -#define SB_GEVENT_REG11 0x6B -#define SB_GEVENT_REG12 0x6C -#define SB_GEVENT_REG13 0x6D -#define SB_GEVENT_REG14 0x6E -#define SB_GEVENT_REG15 0x6F -#define SB_GEVENT_REG16 0x70 -#define SB_GEVENT_REG17 0x71 -#define SB_GEVENT_REG18 0x72 -#define SB_GEVENT_REG19 0x73 -#define SB_GEVENT_REG20 0x74 -#define SB_GEVENT_REG21 0x75 -#define SB_GEVENT_REG22 0x76 -#define SB_GEVENT_REG23 0x77 -// S5-DOMAIN GPIO -#define SB_GPIO_REG160 0xA0 -#define SB_GPIO_REG161 0xA1 -#define SB_GPIO_REG162 0xA2 -#define SB_GPIO_REG163 0xA3 -#define SB_GPIO_REG164 0xA4 -#define SB_GPIO_REG165 0xA5 -#define SB_GPIO_REG166 0xA6 -#define SB_GPIO_REG167 0xA7 -#define SB_GPIO_REG168 0xA8 -#define SB_GPIO_REG169 0xA9 -#define SB_GPIO_REG170 0xAA -#define SB_GPIO_REG171 0xAB -#define SB_GPIO_REG172 0xAC -#define SB_GPIO_REG173 0xAD -#define SB_GPIO_REG174 0xAE -#define SB_GPIO_REG175 0xAF -#define SB_GPIO_REG176 0xB0 -#define SB_GPIO_REG177 0xB1 -#define SB_GPIO_REG178 0xB2 -#define SB_GPIO_REG179 0xB3 -#define SB_GPIO_REG180 0xB4 -#define SB_GPIO_REG181 0xB5 -#define SB_GPIO_REG182 0xB6 -#define SB_GPIO_REG183 0xB7 -#define SB_GPIO_REG184 0xB8 -#define SB_GPIO_REG185 0xB9 -#define SB_GPIO_REG186 0xBA -#define SB_GPIO_REG187 0xBB -#define SB_GPIO_REG188 0xBC -#define SB_GPIO_REG189 0xBD -#define SB_GPIO_REG190 0xBE -#define SB_GPIO_REG191 0xBF -#define SB_GPIO_REG192 0xC0 -#define SB_GPIO_REG193 0xC1 -#define SB_GPIO_REG194 0xC2 -#define SB_GPIO_REG195 0xC3 -#define SB_GPIO_REG196 0xC4 -#define SB_GPIO_REG197 0xC5 -#define SB_GPIO_REG198 0xC6 -#define SB_GPIO_REG199 0xC7 -#define SB_GPIO_REG200 0xC8 -#define SB_GPIO_REG201 0xC9 -#define SB_GPIO_REG202 0xCA -#define SB_GPIO_REG203 0xCB -#define SB_GPIO_REG204 0xCC -#define SB_GPIO_REG205 0xCD -#define SB_GPIO_REG206 0xCE -#define SB_GPIO_REG207 0xCF -#define SB_GPIO_REG208 0xD0 -#define SB_GPIO_REG209 0xD1 -#define SB_GPIO_REG210 0xD2 -#define SB_GPIO_REG211 0xD3 -#define SB_GPIO_REG212 0xD4 -#define SB_GPIO_REG213 0xD5 -#define SB_GPIO_REG214 0xD6 -#define SB_GPIO_REG215 0xD7 -#define SB_GPIO_REG216 0xD8 -#define SB_GPIO_REG217 0xD9 -#define SB_GPIO_REG218 0xDA -#define SB_GPIO_REG219 0xDB -#define SB_GPIO_REG220 0xDC -#define SB_GPIO_REG221 0xDD -#define SB_GPIO_REG222 0xDE -#define SB_GPIO_REG223 0xDF -#define SB_GPIO_REG224 0xF0 -#define SB_GPIO_REG225 0xF1 -#define SB_GPIO_REG226 0xF2 -#define SB_GPIO_REG227 0xF3 -#define SB_GPIO_REG228 0xF4 - -// -// SB800 SB MMIO Base (SMBUS) -// offset : 0xA00 -// -#define SB_SMBUS_REG12 0x12 // I2CbusConfig - -// -// SB800 SB MMIO Base (MISC) -// offset : 0xE00 -// -#define SB_MISC_REG00 0x00 // ClkCntrl0 -/* -SB_MISC_REG00 EQU 000h - ClkCntrl0 EQU 0FFFFFFFFh -*/ -#define SB_MISC_REG04 0x04 // ClkCntrl1 -/* -SB_MISC_REG04 EQU 004h - ClkCntrl1 EQU 0FFFFFFFFh -*/ -#define SB_MISC_REG08 0x08 // ClkCntrl2 -/* -SB_MISC_REG08 EQU 008h - ClkCntrl2 EQU 0FFFFFFFFh -*/ -#define SB_MISC_REG0C 0x0C // ClkCntrl3 -/* -SB_MISC_REG0C EQU 00Ch - ClkCntrl3 EQU 0FFFFFFFFh -*/ -#define SB_MISC_REG10 0x10 // ClkCntrl4 -/* -SB_MISC_REG10 EQU 010h - ClkCntrl4 EQU 0FFFFFFFFh -*/ -#define SB_MISC_REG14 0x14 // ClkCntrl5 -/* -SB_MISC_REG14 EQU 014h - ClkCntrl5 EQU 0FFFFFFFFh -*/ -#define SB_MISC_REG18 0x18 // ClkCntrl6 -/* -SB_MISC_REG18 EQU 018h - ClkCntrl6 EQU 0FFFFFFFFh -*/ -#define SB_MISC_REG30 0x30 // OscFreqCounter -/* -SB_MISC_REG30 EQU 030h - OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second. -*/ -#define SB_MISC_REG34 0x34 // HpetClkPeriod -/* -SB_MISC_REG34 EQU 034h - HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M). -*/ -#define SB_MISC_REG40 0x40 // MiscCntrl for clock only -/* -SB_MISC_REG40 EQU 040h -*/ - -#define SB_MISC_REG80 0x80 /**< SB_MISC_REG80 - * @par - * StrapStatus [15.0] - SB800 chip Strap Status - * @li <b>0001</b> - Not USED FWH - * @li <b>0002</b> - Not USED LPC ROM - * @li <b>0004</b> - EC enabled - * @li <b>0008</b> - Reserved - * @li <b>0010</b> - Internal Clock mode - */ - -#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad -#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1) - // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type. -#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC) -#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function -#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock ** - -#define SB_MISC_REG84 0x84 // StrapOverride -/* -SB_MISC_REG84 EQU 084h - Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin. - Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin. - Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin. - Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin. - Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin. - Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin. - Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin. - Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin. - Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin. - Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin. - Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin' - PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin ?? Not match 0x80 reg ?? - BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin' - ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin. - BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin. - StrapOverrideEn EQU BIT31 ; Enable override strapping feature. -*/ -#define SB_MISC_REGC0 0xC0 // CPU_Pstate0 -/* -SB_MISC_REGC0 EQU 0C0h - Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 - Core1_PState EQU BIT4+BIT5+BIT6 - Core2_PState EQU BIT8+BIT9+BIT10 - Core3_PState EQU BIT12+BIT13+BIT14 - Core4_PState EQU BIT16++BIT17+BIT18 - Core5_PState EQU BIT20+BIT21+BIT22 - Core6_PState EQU BIT24+BIT25+BIT26 - Core7_PState EQU BIT28+BIT29+BIT30 -*/ -#define SB_MISC_REGC4 0xC4 // CPU_Pstate1 -/* -SB_MISC_REGC4 EQU 0C4h - Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 - Core9_PState EQU BIT4+BIT5+BIT6 - Core10_PState EQU BIT8+BIT9+BIT10 - Core11_PState EQU BIT12+BIT13+BIT14 - Core12_PState EQU BIT16++BIT17+BIT18 - Core13_PState EQU BIT20+BIT21+BIT22 - Core14_PState EQU BIT24+BIT25+BIT26 - Core15_PState EQU BIT28+BIT29+BIT30 -*/ -#define SB_MISC_REGD0 0xD0 // CPU_Cstate0 -/* -SB_MISC_REGD0 EQU 0D0h - Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 - Core1_CState EQU BIT4+BIT5+BIT6 - Core2_CState EQU BIT8+BIT9+BIT10 - Core3_CState EQU BIT12+BIT13+BIT14 - Core4_CState EQU BIT16++BIT17+BIT18 - Core5_CState EQU BIT20+BIT21+BIT22 - Core6_CState EQU BIT24+BIT25+BIT26 - Core7_CState EQU BIT28+BIT29+BIT30 -*/ -#define SB_MISC_REGD4 0xD4 // CPU_Cstate1 -/* -SB_MISC_REGD4 EQU 0D4h - Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 - Core9_CState EQU BIT4+BIT5+BIT6 - Core10_CState EQU BIT8+BIT9+BIT10 - Core11_CState EQU BIT12+BIT13+BIT14 - Core12_CState EQU BIT16++BIT17+BIT18 - Core13_CState EQU BIT20+BIT21+BIT22 - Core14_CState EQU BIT24+BIT25+BIT26 - Core15_CState EQU BIT28+BIT29+BIT30 -*/ -#define SB_MISC_REGF0 0xF0 // SataPortSts ?? EC touch only -/* -SB_MISC_REGF0 EQU 0F0h - Port0Sts EQU BIT0 ; The selected status of Port 0. - Port1Sts EQU BIT1 ; The selected status of Port 1 - Port2Sts EQU BIT2 ; The selected status of Port 2. - Port3Sts EQU BIT3 ; The selected status of Port 3 - Port4Sts EQU BIT4 ; The selected status of Port 4. - Port5Sts EQU BIT5 ; The selected status of Port 5 - SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5 - ; 01 - Select "delete" for Port 0 to 5 - ; 10 - Select "err" for Port 0 to 5 - ; 11 - Select "led" for Port 0 to 5 -*/ - - - -#define SB_RTC_REG00 0x00 // Seconds - RW -#define SB_RTC_REG01 0x01 // Seconds Alarm - RW -#define SB_RTC_REG02 0x02 // Minutes - RW -#define SB_RTC_REG03 0x03 // Minutes Alarm - RW -#define SB_RTC_REG04 0x04 // ours - RW -#define SB_RTC_REG05 0x05 // ours Alarm- RW -#define SB_RTC_REG06 0x06 // Day of Week - RW -#define SB_RTC_REG07 0x07 // Date of Mont - RW -#define SB_RTC_REG08 0x08 // Mont - RW -#define SB_RTC_REG09 0x09 // Year - RW -#define SB_RTC_REG0A 0x0A // Register A - RW -#define SB_RTC_REG0B 0x0B // Register B - RW -#define SB_RTC_REG0C 0x0C // Register C - R -#define SB_RTC_REG0D 0x0D // DateAlarm - RW -#define SB_RTC_REG32 0x32 // AltCentury - RW -#define SB_RTC_REG48 0x48 // Century - RW -#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW -#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW -#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW -#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW - -#define SB_ECMOS_REG00 0x00 // scratch - reg -//;BIT0=0 AsicDebug is enabled -//;BIT1=0 SLT S3 runs -#define SB_ECMOS_REG01 0x01 -#define SB_ECMOS_REG02 0x02 -#define SB_ECMOS_REG03 0x03 -#define SB_ECMOS_REG04 0x04 -#define SB_ECMOS_REG05 0x05 -#define SB_ECMOS_REG06 0x06 -#define SB_ECMOS_REG07 0x07 -#define SB_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure -#define SB_ECMOS_REG09 0x09 -#define SB_ECMOS_REG0A 0x0A -#define SB_ECMOS_REG0B 0x0B - -#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID -#define SB_ECMOS_REG0D 0x0D //;Reserve for NB - -#define SB_IOMAP_REG00 0x000 // Dma_C 0 -#define SB_IOMAP_REG02 0x002 // Dma_C 1 -#define SB_IOMAP_REG04 0x004 // Dma_C 2 -#define SB_IOMAP_REG06 0x006 // Dma_C 3 -#define SB_IOMAP_REG08 0x008 // Dma_Status -#define SB_IOMAP_REG09 0x009 // Dma_WriteRest -#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask -#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode -#define SB_IOMAP_REG0C 0x00C // Dma_Clear -#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr -#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask -#define SB_IOMAP_REG0F 0x00F // Dma_AllMask -#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1 -#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2 -#define SB_IOMAP_REG40 0x040 // TimerC0 -#define SB_IOMAP_REG41 0x041 // TimerC1 -#define SB_IOMAP_REG42 0x042 // TimerC2 -#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord -#define SB_IOMAP_REG61 0x061 // Nmi_Status -#define SB_IOMAP_REG70 0x070 // Nmi_Enable -#define SB_IOMAP_REG71 0x071 // RtcDataPort -#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort -#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort -#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0 -#define SB_IOMAP_REG81 0x081 // Dma_PageC2 -#define SB_IOMAP_REG82 0x082 // Dma_PageC3 -#define SB_IOMAP_REG83 0x083 // Dma_PageC1 -#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1 -#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2 -#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3 -#define SB_IOMAP_REG87 0x087 // Dma_PageC0 -#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4 -#define SB_IOMAP_REG89 0x089 // Dma_PageC6 -#define SB_IOMAP_REG8A 0x08A // Dma_PageC7 -#define SB_IOMAP_REG8B 0x08B // Dma_PageC5 -#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5 -#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6 -#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7 -#define SB_IOMAP_REG8F 0x08F // Dma_Refres -#define SB_IOMAP_REG92 0x092 // FastInit -#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1 -#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2 -#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr -#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt -#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr -#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt -#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr -#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt -#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr -#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt -#define SB_IOMAP_REGD0 0x0D0 // Dma_Status -#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest -#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask -#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode -#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear -#define SB_IOMAP_REGDA 0x0DA // Dma_Clear -#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask -#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask -#define SB_IOMAP_REGF0 0x0F0 // NCP_Error -#define SB_IOMAP_REG40B 0x040B // DMA1_Extend -#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl -#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend -#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index -#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data -#define SB_IOMAP_REGC14 0x0C14 // Pci_Error -#define SB_IOMAP_REGC50 0x0C50 // CMIndex -#define SB_IOMAP_REGC51 0x0C51 // CMData -#define SB_IOMAP_REGC52 0x0C52 // GpmPort -#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc -#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index -#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data -#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index -#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data -#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index -#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data -#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg - - -#define SB_SPI_MMIO_REG00 0x00 //SPI_ -#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register - -#define AMD_NB_REG78 0x78 -#define AMD_NB_SCRATCH AMD_NB_REG78 -#define MailBoxPort 0x3E - -// GPP Link Configuration -#define GPP_CFGMODE_X4000 0x0 -#define GPP_CFGMODE_X2200 0x2 -#define GPP_CFGMODE_X2110 0x3 -#define GPP_CFGMODE_X1111 0x4 - -#define MAX_TRAINING_RETRY 0x4000 -#define MAX_GPP_RESETS 8 //lx-temp to confirm with jason - - -#pragma pack (pop) - diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c deleted file mode 100644 index 149e1defce..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ /dev/null @@ -1,1057 +0,0 @@ -/** - * @file - * - * Southbridge Initial routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" -// -// Declaration of local functions -// - -VOID abcfgTbl (IN ABTBLENTRY* pABTbl); - -/** - * sbUsbPhySetting - USB Phy Calibration Adjustment - * - * - * @param[in] Value Controller PCI config address (bus# + device# + function#) - * - */ -VOID sbUsbPhySetting (IN UINT32 Value); - - -/*--------------------------- Documentation Pages ---------------------------*/ -/** - * @page LegacyInterfaceCalls Legacy Interface Calls - * <TD>@subpage SB_POWERON_INIT_Page "SB_POWERON_INIT"</TD><TD></TD> - * <TD>@subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT"</TD><TD></TD> - * <TD>@subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT"</TD><TD></TD> - * <TD>@subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT"</TD><TD></TD> - * <TD>@subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT"</TD><TD></TD> - * <TD>@subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT"</TD><TD></TD> - * <TD>@subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE"</TD><TD></TD> - * <TD>@subpage SB_SMM_ACPION_Page "SB_SMM_ACPION"</TD><TD></TD> - * - * @page LegacyInterfaceCallOuts Legacy Interface CallOuts - * <TD>@subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT - * <TD>@subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT - * -*/ - -/** - * sbEarlyPostByteInitTable - PCI device registers initial during early POST. - * - */ -static const REG8MASK sbEarlyPostByteInitTable[] = -{ - // SMBUS Device (Bus 0, Dev 20, Func 0) - {0x00, SMBUS_BUS_DEV_FUN, 0}, - {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information - {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)}, - {0xFF, 0xFF, 0xFF}, - - // IDE Device (Bus 0, Dev 20, Func 1) - {0x00, IDE_BUS_DEV_FUN, 0}, - {SB_IDE_REG62 + 1, ~BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0 - // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1 - {0xFF, 0xFF, 0xFF}, - - // Azalia Device (Bus 0, Dev 20, Func 2) - {0x00, AZALIA_BUS_DEV_FUN, 0}, - {SB_AZ_REG4C, ~BIT0, BIT0}, - {0xFF, 0xFF, 0xFF}, - - // LPC Device (Bus 0, Dev 20, Func 3) - {0x00, LPC_BUS_DEV_FUN, 0}, - {SB_LPC_REG40, ~BIT2, BIT2}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b - {SB_LPC_REG78, ~BIT0, 00}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b - {SB_LPC_REG78, ~BIT1, 00}, // Disables MSI capability - {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5}, // Enabled SPI Prefetch from HOST. - {0xFF, 0xFF, 0xFF}, - - // PCIB Bridge (Bus 0, Dev 20, Func 4) - {0x00, PCIB_BUS_DEV_FUN, 0}, - {SB_PCIB_REG40, 0xFF, BIT5}, // RPR PCI-bridge Subtractive Decode - {SB_PCIB_REG4B, 0xFF, BIT7}, // - {SB_PCIB_REG66, 0xFF, BIT4}, // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] - {SB_PCIB_REG65, 0xFF, BIT7}, // RPR proper operation of CLKRUN#. - {SB_PCIB_REG0D, 0x00, 0x40}, // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership - {SB_PCIB_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted. - {SB_PCIB_REG66 + 1, 0xFF, BIT1}, // RPR Enable PCI bus GNT3#.. - {0xFF, 0xFF, 0xFF}, - - // SATA Device (Bus 0, Dev 17, Func 0) - {0x00, SATA_BUS_DEV_FUN, 0}, - {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post - {SB_SATA_REG44 + 2, 0, 0x20}, // RPR 8.12 SATA PCI Watchdog timer setting - // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue. - {0xFF, 0xFF, 0xFF}, -}; - - -/** - * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST. - * - */ -static const AcpiRegWrite sbPmioEPostInitTable[] = -{ - // HPET workaround - {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, - {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, BIT7}, - {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, 0x00}, - // End of HPET workaround - // Enable SB800 A12 ACPI bits at PMIO 0xC0 [30,10:3] - // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time. - // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time. - // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood. - // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event. - // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled. - // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit. - // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state. - // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled. - // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support. - {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~(BIT2 + BIT4), BIT2 + BIT4}, - {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9}, - // PM_reg xC1 [3] = 1b, per RPR 2.7 CPU PwrGood Setting - {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x0B}, - // RtcSts 19-17 RTC_STS set only in Sleep State. - // GppPme 20 Set to 1 to enable PME request from SB GPP. - // Pcireset 22 Set to 1 to allow SW to reset PCIe. - {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58}, - {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40}, - - //Item Id: SB02037: RTC_STS should be set in S state - //set PMIO 0xC0 [19:16] Set to 1110 to allow RTC_STS to be set only in non_G0 state. - //{PMIO_BASE >> 8, SB_PMIOA_REGC2, (UINT8)~(0x0F), 0x0E}, - - //Item Id: SB02034 - //Title: SB GPP NIC auto wake at second time sleep - //set PMIO 0xC4 bit 2 to 1 then set PMIO 0xC0 bit 20 to 1 to enable fix for SB02034 - - {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4}, - - //{GPIO_BASE >> 8, SB_GPIO_REG62 , 0x00, 0x4E}, - {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4}, - {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1}, - {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4}, - {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3}, - {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6}, - {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1}, - {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT0 + BIT1), 0}, - //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01 - {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0}, - // RPR Turning off FC clock - {MISC_BASE >> 8, SB_MISC_REG40 + 1, ~(BIT3 + BIT2), BIT3 + BIT2}, - {MISC_BASE >> 8, SB_MISC_REG40 + 2, ~BIT0, BIT0}, - {SMI_BASE >> 8, SB_SMI_Gevent0, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1}, - {SMI_BASE >> 8, SB_SMI_Gevent2, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4}, - {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5}, - {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6}, - {SMI_BASE >> 8, SB_SMI_Gevent7, 0, 29}, - - {SMI_BASE >> 8, SB_SMI_Gevent9, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent10, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent11, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent12, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent13, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent14, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent15, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent16, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent17, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent18, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent19, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent20, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent21, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent22, 0, 29}, - {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 29}, -// - {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11}, - {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11}, - {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11}, - {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11}, - {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12}, - {SMI_BASE >> 8, SB_SMI_IMCGevent1, 0, 29}, - {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13}, - {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15}, - {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16}, - {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17}, - {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18}, - {SMI_BASE >> 8, SB_SMI_SBGppHp0, 0, 29}, - {SMI_BASE >> 8, SB_SMI_SBGppHp1, 0, 29}, - {SMI_BASE >> 8, SB_SMI_SBGppHp2, 0, 29}, - {SMI_BASE >> 8, SB_SMI_SBGppHp3, 0, 29}, - {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19}, - {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 23}, - {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 26}, - {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27}, - {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30}, - {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31}, - - {SMI_BASE >> 8, SB_SMI_WakePinGevent, 0, 29}, - {SMI_BASE >> 8, SB_SMI_ASFMasterIntr, 0, 29}, - {SMI_BASE >> 8, SB_SMI_ASFSlaveIntr, 0, 29}, - -// {SMI_BASE >> 8, SB_SMI_REG04, ~BIT4, BIT4}, -// {SMI_BASE >> 8, SB_SMI_REG04 + 1, ~BIT0, BIT0}, -// {SMI_BASE >> 8, SB_SMI_REG04 + 2, ~BIT3, BIT3}, - {SMI_BASE >> 8, SB_SMI_REG08, ~BIT4, 0}, - {SMI_BASE >> 8, SB_SMI_REG08+3, ~BIT2, 0}, -// {SMI_BASE >> 8, SB_SMI_REG0C, ~BIT4, BIT4}, - {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3}, - {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9}, - {SMI_BASE >> 8, SB_SMI_TMI, 0, 29}, - {0xFF, 0xFF, 0xFF, 0xFF}, -}; - -/** - * abTblEntry800 - AB-Link Configuration Table for SB800 - * - */ -static const ABTBLENTRY abTblEntry800[] = -{ - // RPR Enable downstream posted transactions to pass non-posted transactions. - {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, - - // RPR Enable SB800 to issue memory read/write requests in the upstream direction. - {AXCFG, SB_AB_REG04, BIT2, BIT2}, - - // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement - // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1 - {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, // PCIB prefetch enable - {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, // PCIB prefetch enable - - // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices. - // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11) - {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18}, - - // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21] - // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17] - {ABCFG, SB_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17}, - - // RPR Disable the credit variable in the downstream arbitration equation - // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set) - {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0}, - - // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1 - // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20] - {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE}, - - // RPR Programming cycle delay for AB and BIF clock gating - // RPR Enable the AB and BIF clock-gating logic. - // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently - // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP - {ABCFG, SB_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF}, - {ABCFG, SB_ABCFG_REG98, 0xFFFF00FF, 0x00034700}, - {ABCFG, SB_ABCFG_REG54, 0x00FF0000, 0x00040000}, - // RPR Non-Posted Memory Write Support - {AX_INDXC, SB_AX_INDXC_REG10, BIT9, BIT9}, - {ABCFG, 0, 0, (UINT8) 0xFF}, // This dummy entry is to clear ab index - { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, -}; - -/** - * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature - * - */ -static const ABTBLENTRY SbPcieOrderRule[] = -{ -// abPostPassNpDownStreamTbl - {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31}, - {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5}, - {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7}, - {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23}, - {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5}, - {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9}, - {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12}, -// abPostPassNpUpStreamTbl - {ABCFG, SB_ABCFG_REG58, BIT10, BIT10}, - {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4}, - {ABCFG, SB_ABCFG_REG54, BIT1, BIT1}, - { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF}, -}; - -/** - * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. - * - * This settings should be done during S3 resume also - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -commonInitEarlyBoot ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 abValue; - UINT16 dwTempVar; - CPUID_DATA CpuId; - UINT8 cimIrConfig; - UINT8 Data; - - cimIrConfig = (UINT8) pConfig->IrConfig; -#if SB_CIMx_PARAMETER == 0 - cimIrConfig = cimIrConfigDefault; -#endif - - //IR init Logical device 0x05 - if ( cimIrConfig ) { - // Enable EC_PortActive - RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0); - EnterEcConfig (); - RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller - RWEC8 (0x60, 0x00, 0x05); //Set Base Address to 550h - RWEC8 (0x61, 0x00, 0x50); - RWEC8 (0x70, 0xF0, 0x05); //Set IRQ to 05h - RWEC8 (0x30, 0x00, 0x01); //Enable logical device 5, IR controller - Data = 0xAB; - WriteIO (0x550, AccWidthUint8, &Data); - ReadIO (0x551, AccWidthUint8, &Data); - Data = ((Data & 0xFC ) | cimIrConfig); - WriteIO (0x551, AccWidthUint8, &Data); - ExitEcConfig (); - Data = 0xA0; // EC APIC index - WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data); - Data = 0x05; // IRQ5 - WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data); - } else { - EnterEcConfig (); - RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller - RWEC8 (0x30, 0x00, 0x00); //Disable logical device 5, IR controller - ExitEcConfig (); - } - - - CpuidRead (0x01, &CpuId); - - // - // SB CFG programming - // - //Make BAR registers of smbus visible. - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); - //Early post initialization of pci config space - programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); - if ( pConfig->BuildParameters.SmbusSsid != 0 ) { - RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); - } - //Make BAR registers of smbus invisible. - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6); - - // - // LPC CFG programming - // - // SSID for LPC Controller - if (pConfig->BuildParameters.LpcSsid != 0 ) { - RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid); - } - // LPC MSI - if ( pConfig->BuildParameters.LpcMsi) { - RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1); - } - - // - // PCIB CFG programming - // - //Disable or Enable PCI Clks based on input - RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), ((pConfig->PciClks) & 0x0F) << 2 ); - RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), (pConfig->PciClks) >> 4 ); - // PCIB MSI - if ( pConfig->BuildParameters.PcibMsi) { - RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3); - } - - // - // AB CFG programming - // - // Read Arbiter address, Arbiter address is in PMIO 6Ch - ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar); - RWIO (dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter - - abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers - // AB MSI - if ( pConfig->BuildParameters.AbMsi) { - abValue = readAlink (SB_ABCFG_REG94 | ((UINT32) ABCFG << 29)); - abValue = abValue | BIT20; - writeAlink (SB_ABCFG_REG94 | ((UINT32) ABCFG << 29), abValue); - } - - - // - // SB Specific Function programming - // - - // PCIE Native setting - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0); - if ( pConfig->NativePcieSupport == 1) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2 + BIT0); - } else { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2); - } - -#ifdef ACPI_SLEEP_TRAP - // Set SLP_TYPE as SMI event - RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2); - // Disabled SLP function for S1/S3/S4/S5 - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00); - // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1) - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1); - // Enabled Global Smi ( BIT7 clear as 0 to enable ) - RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00); -#endif - if ( pConfig->SbUsbPll == 0) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20); - } - // Set Stutter timer settings - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4); - // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz - if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x28); - } else { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x20); - } - - //PM_Reg 0x7A[15] (CountHaltMsgEn) should be set when C1e option is enabled - //PM_Reg 0x7A[3:0] (NumOfCpu) should be set to 1h when C1e option is enabled - //PM_Reg 0x80[13] has to set to 1 to enable Message C scheme. - if (pConfig->MTC1e) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, 0x7FF0, BIT15 + 1); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5); - } - - programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); -} - -/** - * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -abSpecialSetBeforePciEnum ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 abValue; - abValue = readAlink (SB_ABCFG_REGC0 | ((UINT32) ABCFG << 29)); - abValue &= 0xf0; - if ( pConfig->SbPcieOrderRule && abValue ) { - abValue = readAlink (SB_RCINDXC_REG02 | ((UINT32) RCINDXC << 29)); - abValue = abValue | BIT9; - writeAlink (SB_RCINDXC_REG02 | ((UINT32) RCINDXC << 29), abValue); - } -} - -VOID -usbDesertPll ( - IN AMDSBCFG* pConfig - ) -{ - if ( pConfig->SbUsbPll == 0) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00); - } -} - -/** - * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. - * - * This settings might not program during S3 resume - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -commonInitEarlyPost ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 dbPortStatus; - UINT8 cimSpreadSpectrum; - UINT32 cimSpreadSpectrumType; - - cimSpreadSpectrum = pConfig->SpreadSpectrum; - cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType; -#if SB_CIMx_PARAMETER == 0 - cimSpreadSpectrum = cimSpreadSpectrumDefault; - cimSpreadSpectrumType = cimSpreadSpectrumTypeDefault; -#endif - programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0])); - - // CallBackToOEM (PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig); - - if ( cimSpreadSpectrum ) { - // Misc_Reg_40[25]=1 -> allow to change spread profile - // Misc_Reg19=83 -> new spread profile - // Misc_Reg[12:10]=9975be - // Misc_Reg0B=91 - // Misc_Reg09=21 - // Misc_Misc_Reg_08[0]=1 -> enable spread - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83); - getChipSysMode (&dbPortStatus); - if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) { - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80); - } - - if ( cimSpreadSpectrumType == 0 ) { - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21); - } else { // Spread profile for Ontario CPU related platform - // This spread profile setting is for Ontario HDMI & DVI output from DP with -0.425% - // Misc_Reg[12:10]=828FA8 - // Misc_Reg0B=11 - // Misc_Reg09=21 - // Misc_Reg10[25:24]=01b - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x82); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x8F); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xA8); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x11); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x1); - } - - RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01); - } else { - RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00); - } - - // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode - getChipSysMode (&dbPortStatus); - if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) { - RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04 + 1, AccWidthUint8, ~BIT5, BIT5); - } - - // Set ASF SMBUS master function enabled here (temporary) - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2); - - programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); -#ifndef NO_EC_SUPPORT - // Software IMC enable - if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) { - if (validateImcFirmware (pConfig)) { - softwareToggleImcStrapping (pConfig); - } else { - CallBackToOEM (IMC_FIRMWARE_FAIL, 0, pConfig); - } - } -#endif - -} -/** - * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -abLinkInitBeforePciEnum ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 cimResetCpuOnSyncFlood; - ABTBLENTRY *pAbTblPtr; - - cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood; -#if SB_CIMx_PARAMETER == 0 - cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault; -#endif - if ( pConfig->SbPcieOrderRule ) { - pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]); - abcfgTbl (pAbTblPtr); - } - pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]); - abcfgTbl (pAbTblPtr); - if ( cimResetCpuOnSyncFlood ) { - rwAlink (SB_ABCFG_REG10050 | ((UINT32) ABCFG << 29), ~BIT2, BIT2); - } -} - -/** - * abcfgTbl - Program ABCFG by input table. - * - * - * @param[in] pABTbl ABCFG config table. - * - */ -VOID -abcfgTbl ( - IN ABTBLENTRY* pABTbl - ) -{ - UINT32 ddValue; - - while ( (pABTbl->regType) != 0xFF ) { - if ( pABTbl->regType > AXINDC ) { - ddValue = pABTbl->regIndex | ((UINT32) pABTbl->regType << 29); - writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData); - } else { - ddValue = 0x30 | ((UINT32) pABTbl->regType << 29); - writeAlink (ddValue, pABTbl->regIndex); - ddValue = 0x34 | ((UINT32) pABTbl->regType << 29); - writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData); - } - ++pABTbl; - } - - //Clear ALink Access Index - ddValue = 0; - WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue); -} - -/** - * commonInitLateBoot - Prepare Southbridge register setting to boot to OS. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -commonInitLateBoot ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 dbValue; - UINT32 ddVar; - // We need to do the following setting in late post also because some bios core pci enumeration changes these values - // programmed during early post. - // RPR 4.5 Master Latency Timer - - dbValue = 0x40; - WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue); - WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue); - - //SB P2P AutoClock control settings. - ddVar = (pConfig->PcibAutoClkCtrlHigh << 16) | (pConfig->PcibAutoClkCtrlLow); - WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar); - ddVar = (pConfig->PcibClkStopOverride); - RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6)); - - RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5); - - // USB Phy Calibration Adjustment - ddVar = (USB1_EHCI_BUS_DEV_FUN << 16); - sbUsbPhySetting (ddVar); - ddVar = (USB2_EHCI_BUS_DEV_FUN << 16); - sbUsbPhySetting (ddVar); - ddVar = (USB3_EHCI_BUS_DEV_FUN << 16); - sbUsbPhySetting (ddVar); - - c3PopupSetting (pConfig); - FusionRelatedSetting (pConfig); -} - -/** - * sbUsbPhySetting - USB Phy Calibration Adjustment - * - * - * @param[in] Value Controller PCI config address (bus# + device# + function#) - * - */ -VOID -sbUsbPhySetting ( - IN UINT32 Value - ) -{ - UINT32 ddBarAddress; - UINT32 ddPhyStatus03; - UINT32 ddPhyStatus4; - UINT8 dbRevId; - //Get BAR address - ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress); - if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { - ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGA8, AccWidthUint32, &ddPhyStatus03); - ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGAC, AccWidthUint32, &ddPhyStatus4); - ddPhyStatus03 &= 0x07070707; - ddPhyStatus4 &= 0x00000007; - if ( (ddPhyStatus03 != 0x00) | (ddPhyStatus4 != 0x00) ) { - // RPR 7.7 USB 2.0 Ports Driving Strength step 1 - //Make BAR registers of smbus visible. - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); - ReadPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08, AccWidthUint8, &dbRevId); - //Make BAR registers of smbus invisible. - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6); - if (dbRevId == 0x41) { // A12 - RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x1500); - RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0); - } else if (dbRevId == 0x42) { // A13 - RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x0F00); - RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0x0100); - } - } - } -} - -/** - * hpetInit - Program Southbridge HPET function - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * @param[in] pStaticOptions Platform build configuration table. - * - */ -VOID -hpetInit ( - IN AMDSBCFG* pConfig, - IN BUILDPARAM *pStaticOptions - ) -{ - DESCRIPTION_HEADER* pHpetTable; - UINT8 cimHpetTimer; - UINT8 cimHpetMsiDis; - - cimHpetTimer = (UINT8) pConfig->HpetTimer; - cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis; -#if SB_CIMx_PARAMETER == 0 - cimHpetTimer = cimHpetTimerDefault; - cimHpetMsiDis = cimHpetMsiDisDefault; -#endif - pHpetTable = NULL; - if ( cimHpetTimer == TRUE ) { - //Program the HPET BAR address - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase); - //Enabling decoding of HPET MMIO - //Enable HPET MSI support - //Enable High Precision Event Timer (also called Multimedia Timer) interrupt - if ( cimHpetMsiDis == FALSE ) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4); - } else { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1); - } - - } else { - if ( ! (pConfig->S3Resume) ) { - pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (Int32FromChar('H', 'P', 'E', 'T')); - } - if ( pHpetTable != NULL ) { - pHpetTable->Signature = Int32FromChar('T', 'E', 'P', 'H'); - } - } -} - -/** - * c3PopupSetting - Program Southbridge C state function - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -c3PopupSetting ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 dbValue; - //RPR C-State and VID/FID Change - dbValue = getNumberOfCpuCores (); - if (dbValue > 1) { - //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated. - //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD - //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert - //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time. - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6); - } - //SB800 needs to changed for RD790 support - //PM 0x80 [8] = 0 for system with RS780 - //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link. - //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle. - //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F); - //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that - //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also - //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT - //link is disconnected. - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10); - - //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The - //delay will allow USB DMA to go on in a continuous manner - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10); - // Not in the RPR so far, it's hand writing from ASIC - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4); - // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, 0xFF, BIT4); - if (pConfig->LdtStpDisable) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT5, 0); - } -} - -/** - * FusionRelatedSetting - Program Fusion C related function - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -FusionRelatedSetting ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 cimAcDcMsg; - UINT8 cimTimerTickTrack; - UINT8 cimClockInterruptTag; - UINT8 cimOhciTrafficHanding; - UINT8 cimEhciTrafficHanding; - UINT8 cimFusionMsgCMultiCore; - UINT8 cimFusionMsgCStage; - UINT32 ddValue; - - cimAcDcMsg = (UINT8) pConfig->AcDcMsg; - cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack; - cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag; - cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding; - cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding; - cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore; - cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage; -#if SB_CIMx_PARAMETER == 0 - cimAcDcMsg = cimAcDcMsgDefault; - cimTimerTickTrack = cimTimerTickTrackDefault; - cimClockInterruptTag = cimClockInterruptTagDefault; - cimOhciTrafficHanding = cimOhciTrafficHandingDefault; - cimEhciTrafficHanding = cimEhciTrafficHandingDefault; - cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault; - cimFusionMsgCStage = cimFusionMsgCStageDefault; -#endif - ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue); - ddValue = ddValue & 0xC07F00A0; - if ( cimAcDcMsg ) { - ddValue = ddValue | BIT0; - } - if ( cimTimerTickTrack ) { - ddValue = ddValue | BIT1; - } - if ( cimClockInterruptTag ) { - ddValue = ddValue | BIT10; - } - if ( cimOhciTrafficHanding ) { - ddValue = ddValue | BIT13; - } - if ( cimEhciTrafficHanding ) { - ddValue = ddValue | BIT15; - } - if ( cimFusionMsgCMultiCore ) { - ddValue = ddValue | BIT23; - } - if ( cimFusionMsgCStage ) { - ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2)); - } - WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue); -} -#ifndef NO_EC_SUPPORT -/** - * validateImcFirmware - Validate IMC Firmware. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - * @retval TRUE Pass - * @retval FALSE Failed - */ -BOOLEAN -validateImcFirmware ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ImcSig; - UINT32 ImcSigAddr; - UINT32 ImcAddr; - UINT32 CurAddr; - UINT32 ImcBinSig0; - UINT32 ImcBinSig1; - UINT16 ImcBinSig2; - UINT8 dbIMCChecksume; - UINT8 dbIMC; - ImcAddr = 0; - - // Software IMC enable - ImcSigAddr = 0x80000; // start from 512k to 64M - ImcSig = 0x0; // - while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) { - CurAddr = 0xffffffff - ImcSigAddr + 0x20001; - ReadMEM (CurAddr, AccWidthUint32, &ImcSig); - ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr); - ImcSigAddr <<= 1; - } - - dbIMCChecksume = 0xff; - if ( ImcSig == 0x55aa55aa ) { - // "_AMD_IMC_C" at offset 0x2000 of the binary - ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0); - ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1); - ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2); - if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) { - dbIMCChecksume = 0; - for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) { - ReadMEM (CurAddr, AccWidthUint8, &dbIMC); - dbIMCChecksume = dbIMCChecksume + dbIMC; - } - } - } - if ( dbIMCChecksume ) { - return FALSE; - } else { - return TRUE; - } -} - -/** - * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -softwareToggleImcStrapping ( - IN AMDSBCFG* pConfig - ) -{ - UINT8 dbValue; - UINT8 dbPortStatus; - UINT32 abValue; - UINT32 abValue1; - - getChipSysMode (&dbPortStatus); - - ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue); - //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1 - //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference. - - //StrapStatus StrapOverride - // bit4 bit17 - // bit6 bit12 - // bit12 bit15 - // bit15 bit16 - // bit16 bit18 - ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue); - abValue1 = abValue; - if (abValue & BIT4) { - abValue1 = (abValue1 & ~BIT4) | BIT17; - } - if (abValue & BIT6) { - abValue1 = (abValue1 & ~BIT6) | BIT12; - } - if (abValue & BIT12) { - abValue1 = (abValue1 & ~BIT12) | BIT15; - } - if (abValue & BIT15) { - abValue1 = (abValue1 & ~BIT15) | BIT16; - } - if (abValue & BIT16) { - abValue1 = (abValue1 & ~BIT16) | BIT18; - } - abValue1 |= BIT31; // Overwrite enable - if ((dbPortStatus & ChipSysEcEnable) == 0) { - abValue1 |= BIT2; // bit2- EcEnableStrap - } else { - abValue1 &= ~BIT2; // bit2=0 EcEnableStrap - } - WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1); - dbValue |= BIT6; // PwrGoodOut =1 - dbValue &= ~BIT7; // PwrGoodEnB =0 - WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue); - - dbValue = 06; - WriteIO (0xcf9, AccWidthUint8, &dbValue); - SbStall (0xffffffff); -} -#endif - -#ifndef NO_HWM_SUPPORT -/** - * validateImcFirmware - Validate IMC Firmware. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -hwmInit ( - IN AMDSBCFG* pConfig - ) -{ - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8 | S3_SAVE, 0, 0x55); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8 | S3_SAVE, 0, 0x55); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8 | S3_SAVE, 0, 0x55); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8 | S3_SAVE, 0, 0x55); - - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8 | S3_SAVE, 0, 0x06); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8 | S3_SAVE, 0, 0x06); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8 | S3_SAVE, 0, 0x06); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8 | S3_SAVE, 0, 0x06); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8 | S3_SAVE, 0, 0x06); - - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8 | S3_SAVE, 0, 0x01); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8 | S3_SAVE, 0, 0x01); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8 | S3_SAVE, 0, 0x01); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8 | S3_SAVE, 0, 0x01); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8 | S3_SAVE, 0, 0x01); - - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8 | S3_SAVE, 0, 0x05); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8 | S3_SAVE, 0, 0x06); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8 | S3_SAVE, 0, 0x42); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8 | S3_SAVE, 0, 0xFF); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8 | S3_SAVE, 0, 0x1F); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8 | S3_SAVE, 0, 0x04); - RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8 | S3_SAVE, 0, 0x00); -} -#endif diff --git a/src/vendorcode/amd/cimx/sb800/SBDEF.h b/src/vendorcode/amd/cimx/sb800/SBDEF.h deleted file mode 100644 index 79310fd3d5..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SBDEF.h +++ /dev/null @@ -1,261 +0,0 @@ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -//AMD Library Routines (AMDLIB.C) -unsigned char getNumberOfCpuCores (OUT void); -unsigned int readAlink (IN unsigned int Index); -void writeAlink (IN unsigned int Index, IN unsigned int Data); -void rwAlink (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask); - -//AMD Library Routines (LEGACY.C) -unsigned int GetFixUp (OUT void); - -//AMD Library Routines (IOLIB.C) -void ReadIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value); -void WriteIO (IN unsigned short Address, IN unsigned char OpFlag, IN void *Value); -void RWIO (IN unsigned short Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data); - - - -//AMD Library Routines (MEMLIB.C) -void ReadMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value); -void WriteMEM (IN unsigned int Address, IN unsigned char OpFlag, IN void* Value); -void RWMEM (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data); - -//AMD Library Routines (PCILIB.C) -void ReadPCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value); -void WritePCI (IN unsigned int Address, IN unsigned char OpFlag, IN void *Value); -void RWPCI (IN unsigned int Address, IN unsigned char OpFlag, IN unsigned int Mask, IN unsigned int Data); - -//AMD Library Routines (SBPELIB.C) -/** - * Read Southbridge Revision ID cie Base - * - * - * @retval 0xXXXXXXXX Revision ID - * - */ -unsigned char getRevisionID (OUT void); - -/** - * programPciByteTable - Program PCI register by table (8 bits data) - * - * - * - * @param[in] pPciByteTable - Table data pointer - * @param[in] dwTableSize - Table length - * - */ -void programPciByteTable (IN REG8MASK* pPciByteTable, IN unsigned short dwTableSize); - -/** - * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data) - * - * - * - * @param[in] pAcpiTbl - Table data pointer - * - */ -void programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl); - -/** - * getChipSysMode - Get Chip status - * - * - * @param[in] Value - Return Chip strap status - * StrapStatus [15.0] - SB800 chip Strap Status - * @li <b>0001</b> - Not USED FWH - * @li <b>0002</b> - Not USED LPC ROM - * @li <b>0004</b> - EC enabled - * @li <b>0008</b> - Reserved - * @li <b>0010</b> - Internal Clock mode - * - */ -void getChipSysMode (IN void* Value); - -/** - * Read Southbridge CIMx configuration structure pointer - * - * - * - * @retval 0xXXXXXXXX CIMx configuration structure pointer. - * - */ -AMDSBCFG* getConfigPointer (OUT void); - -//AMD Library Routines (PMIOLIB.C) -/** - * Read PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Read Data Buffer - * - */ -void ReadPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value); - -/** - * Write PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Write Data Buffer - * - */ -void WritePMIO (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value); - -/** - * RWPMIO - Read/Write PMIO - * - * - * - * @param[in] Address - PMIO Offset value - * @param[in] OpFlag - Access sizes - * @param[in] AndMask - Data And Mask 32 bits - * @param[in] OrMask - Data OR Mask 32 bits - * - */ -void RWPMIO (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask); - -//AMD Library Routines (PMIO2LIB.C) - -/** - * Read PMIO2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Read Data Buffer - * - */ -void ReadPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value); - -/** - * Write PMIO 2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] Value - Write Data Buffer - * - */ -void WritePMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN void* Value); - -/** - * RWPMIO2 - Read/Write PMIO2 - * - * - * - * @param[in] Address - PMIO2 Offset value - * @param[in] OpFlag - Access sizes - * @param[in] AndMask - Data And Mask 32 bits - * @param[in] OrMask - Data OR Mask 32 bits - * - */ -void RWPMIO2 (IN unsigned char Address, IN unsigned char OpFlag, IN unsigned int AndMask, IN unsigned int OrMask); -//AMD Library Routines (ECLIB.C) -// ECLIB Routines - -// #ifndef NO_EC_SUPPORT - -/** - * EnterEcConfig - Force EC into Config mode - * - * - * - * - */ -void EnterEcConfig (void); - -/** - * ExitEcConfig - Force EC exit Config mode - * - * - * - * - */ -void ExitEcConfig (void); - -/** - * ReadEC8 - Read EC register data - * - * - * - * @param[in] Address - EC Register Offset Value - * @param[in] Value - Read Data Buffer - * - */ -void ReadEC8 (IN unsigned char Address, IN unsigned char* Value); - -/** - * WriteEC8 - Write date into EC register - * - * - * - * @param[in] Address - EC Register Offset Value - * @param[in] Value - Write Data Buffer - * - */ -void WriteEC8 (IN unsigned char Address, IN unsigned char* Value); - -/** - * RWEC8 - Read/Write EC register - * - * - * - * @param[in] Address - EC Register Offset Value - * @param[in] AndMask - Data And Mask 8 bits - * @param[in] OrMask - Data OR Mask 8 bits - * - */ -void RWEC8 (IN unsigned char Address, IN unsigned char AndMask, IN unsigned char OrMask); - -/** - * IsZoneFuncEnable - check every zone support function with BitMap from user define - * - */ -unsigned char IsZoneFuncEnable ( unsigned short Flag, unsigned char func, unsigned char Zone); - -void sbECfancontrolservice (IN AMDSBCFG* pConfig); -void SBIMCFanInitializeS3 (void); -void GetSbAcpiMmioBase (OUT unsigned int* AcpiMmioBase); -void GetSbAcpiPmBase (OUT unsigned short* AcpiPmBase); - -// #endif - diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c deleted file mode 100644 index 04716bc535..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c +++ /dev/null @@ -1,250 +0,0 @@ -/** - * @file - * - * SB Initialization. - * - * Init IOAPIC/IOMMU/Misc NB features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -/*----------------------------------------------------------------------------------------*/ -/** - * sbBeforePciInit - Config Southbridge before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - -VOID -sbBeforePciInit ( - IN AMDSBCFG* pConfig - ) -{ - commonInitEarlyBoot (pConfig); - commonInitEarlyPost (pConfig); -#ifndef NO_EC_SUPPORT - ecInitBeforePciEnum (pConfig); -#endif - usbInitBeforePciEnum (pConfig); // USB POST TIME Only - sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY - gecInitBeforePciEnum (pConfig); // Init GEC - azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio - sbPcieGppEarlyInit (pConfig); // Gpp port init - abSpecialSetBeforePciEnum (pConfig); - usbDesertPll (pConfig); -} - -/** - * sbAfterPciInit - Config Southbridge after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sbAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - usbInitAfterPciInit (pConfig); // Init USB MMIO - sataInitAfterPciEnum (pConfig); // SATA port enumeration - gecInitAfterPciEnum (pConfig); - azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio - -#ifndef NO_HWM_SUPPORT - hwmInit (pConfig); -#endif -} - -/** - * sbMidPostInit - Config Southbridge during middle of POST - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sbMidPostInit ( - IN AMDSBCFG* pConfig - ) -{ - sataInitMidPost (pConfig); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * sbLatePost - Prepare Southbridge to boot to OS. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sbLatePost ( - IN AMDSBCFG* pConfig - ) -{ -// UINT16 dwVar; - BUILDPARAM *pStaticOptions; - pStaticOptions = &(pConfig->BuildParameters); - commonInitLateBoot (pConfig); - sataInitLatePost (pConfig); - gecInitLatePost (pConfig); - hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit -#ifndef NO_EC_SUPPORT - ecInitLatePost (pConfig); -#endif - sbPcieGppLateInit (pConfig); - -} - -/*----------------------------------------------------------------------------------------*/ -/** - * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - -VOID -sbBeforePciRestoreInit ( - IN AMDSBCFG* pConfig - ) -{ - pConfig->S3Resume = 1; - commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB - abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers - usbInitBeforePciEnum (pConfig); // USB POST TIME Only - sataInitBeforePciEnum (pConfig); - gecInitBeforePciEnum (pConfig); // Init GEC - azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio - sbPcieGppEarlyInit (pConfig); // Gpp port init - abSpecialSetBeforePciEnum (pConfig); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - -VOID -sbAfterPciRestoreInit ( - IN AMDSBCFG* pConfig - ) -{ - BUILDPARAM *pStaticOptions; - - pConfig->S3Resume = 1; - - usbSetPllDuringS3 (pConfig); - pStaticOptions = &(pConfig->BuildParameters); - commonInitLateBoot (pConfig); - sataInitAfterPciEnum (pConfig); - gecInitAfterPciEnum (pConfig); - azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio - hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit - sataInitLatePost (pConfig); - c3PopupSetting (pConfig); - -#ifndef NO_HWM_SUPPORT - SBIMCFanInitializeS3 (); -#endif -} - -/*----------------------------------------------------------------------------------------*/ -/** - * sbSmmAcpiOn - Config Southbridge during ACPI_ON - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sbSmmAcpiOn ( - IN AMDSBCFG* pConfig - ) -{ - // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest - // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows - - // Disable Power Button SMI - RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0); - RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6 + BIT7), 0); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Call Back routine. - * - * - * - * @param[in] Func Callback ID. - * @param[in] Data Callback specific data. - * @param[in] pConfig Southbridge configuration structure pointer. - */ -UINT32 -CallBackToOEM ( - IN UINT32 Func, - IN UINT32 Data, - IN AMDSBCFG* pConfig - ) -{ - UINT32 Result; - Result = 0; - if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result; - Result = (pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig); - - return Result; -} diff --git a/src/vendorcode/amd/cimx/sb800/SBPELIB.c b/src/vendorcode/amd/cimx/sb800/SBPELIB.c deleted file mode 100644 index 403f21fa84..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SBPELIB.c +++ /dev/null @@ -1,198 +0,0 @@ -/** - * @file - * - * Southbridge IO access common routine - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -/** - * Read Southbridge Revision ID cie Base - * - * - * @retval 0xXXXXXXXX Revision ID - * - */ -UINT8 -getRevisionID ( - OUT VOID - ) -{ - UINT8 dbVar0; - ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0); - return dbVar0; -} - -/*----------------------------------------------------------------------------------------*/ -/** - * programPciByteTable - Program PCI register by table (8 bits data) - * - * - * - * @param[in] pPciByteTable - Table data pointer - * @param[in] dwTableSize - Table length - * - */ -VOID -programPciByteTable ( - IN REG8MASK* pPciByteTable, - IN UINT16 dwTableSize - ) -{ - UINT8 i; - UINT8 dbBusNo; - UINT8 dbDevFnNo; - UINT32 ddBDFR; - - dbBusNo = pPciByteTable->bRegIndex; - dbDevFnNo = pPciByteTable->bANDMask; - pPciByteTable++; - - for ( i = 1; i < dwTableSize; i++ ) { - if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) { - pPciByteTable++; - dbBusNo = pPciByteTable->bRegIndex; - dbDevFnNo = pPciByteTable->bANDMask; - pPciByteTable++; - i++; - } else { - ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ; - RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask); - pPciByteTable++; - } - } -} - -/*----------------------------------------------------------------------------------------*/ -/** - * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data) - * - * - * - * @param[in] pAcpiTbl - Table data pointer - * - */ -VOID -programSbAcpiMmioTbl ( - IN AcpiRegWrite *pAcpiTbl - ) -{ - UINT8 i; - UINT32 ddtempVar; - if (pAcpiTbl != NULL) { - for ( i = 1; pAcpiTbl->MmioBase < 0xf0; i++ ) { - ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; - RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask); - pAcpiTbl++; - } - } -} - -/** - * getChipSysMode - Get Chip status - * - * - * @param[in] Value - Return Chip strap status - * StrapStatus [15.0] - SB800 chip Strap Status - * @li <b>0001</b> - Not USED FWH - * @li <b>0002</b> - Not USED LPC ROM - * @li <b>0004</b> - EC enabled - * @li <b>0008</b> - Reserved - * @li <b>0010</b> - Internal Clock mode - * - */ -VOID -getChipSysMode ( - IN VOID* Value - ) -{ - ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value); -} - -/*----------------------------------------------------------------------------------------*/ -/** - * Read Southbridge CIMx configuration structure pointer - * - * - * - * @retval 0xXXXXXXXX CIMx configuration structure pointer. - * - */ -AMDSBCFG* -getConfigPointer ( - OUT VOID - ) -{ - UINT8 dbReg; - UINT8 dbValue; - UINT8 i; - UINT32 ddValue; - ddValue = 0; - dbReg = SB_ECMOS_REG08; - - for ( i = 0; i <= 3; i++ ) { - WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg); - ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue); - ddValue |= (dbValue << (i * 8)); - dbReg++; - } - return ( (AMDSBCFG*) (UINTN)ddValue); -} - -/** - * getEfuseStatue - Get Efuse status - * - * - * @param[in] Value - Return Chip strap status - * - */ -VOID -getEfuseStatus ( - IN VOID* Value - ) -{ - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5); - WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value); - ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0); -} diff --git a/src/vendorcode/amd/cimx/sb800/SBPort.c b/src/vendorcode/amd/cimx/sb800/SBPort.c deleted file mode 100644 index ae1d779e73..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SBPort.c +++ /dev/null @@ -1,364 +0,0 @@ - -/** - * @file - * - * Southbridge Init during POWER-ON - * - * Prepare Southbridge environment during power on stage. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" -/** - * sbPorInitPciTable - PCI device registers initial during the power on stage. - */ -static const REG8MASK sbPorInitPciTable[] = -{ - // SATA device - {0x00, SATA_BUS_DEV_FUN, 0}, - {SB_SATA_REG84 + 3, ~BIT2, 0}, - {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5}, - {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5}, - {0xFF, 0xFF, 0xFF}, - // LPC Device (Bus 0, Dev 20, Func 3) - {0x00, LPC_BUS_DEV_FUN, 0}, - {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2}, - {SB_LPC_REG7C, 0x00, BIT0 + BIT2}, - {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5}, - // A12 set 0xBB [5:3] = 111 to improve SPI timing margin. - // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement) - {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5}, - {SB_LPC_REGBA, 0x9F, BIT5 + BIT6}, - {0xFF, 0xFF, 0xFF}, - // P2P Bridge (Bus 0, Dev 20, Func 4) - {0x00, PCIB_BUS_DEV_FUN, 0}, - {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, - // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge. - {SB_PCIB_REG1C, 0x00, 0xF0}, - {SB_PCIB_REG1D, 0x00, 0x00}, - {SB_PCIB_REG04, 0x00, 0x21}, - {SB_PCIB_REG40, 0xDF, 0x20}, - {SB_PCIB_REG50, 0x02, 0x01}, - {0xFF, 0xFF, 0xFF}, -}; - -/** - * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. - */ -static const AcpiRegWrite sbPmioPorInitTable[] = -{ - {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, - {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, - {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0}, - {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0}, - {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7}, - {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0}, - {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E}, - {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40}, - {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08}, - {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1}, - {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1}, - {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2}, - {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4}, - {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0}, - {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7}, - {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1}, - {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3}, - {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00}, - // RPR GEC I/O Termination Setting - // PM_Reg 0xF6 = Power-on default setting - // PM_Reg 0xF7 = Power-on default setting - // PM_Reg 0xF8 = 0x6C - // PM_Reg 0xF9 = 0x21 - // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS - {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C}, - {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27}, - {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00}, - {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14}, - {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40}, - - {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR - - {0xFF, 0xFF, 0xFF, 0xFF}, -}; - -/** - * sbPowerOnInit - Config Southbridge during power on stage. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sbPowerOnInit ( - IN AMDSBCFG* pConfig - ) -{ - - UINT8 dbPortStatus; - UINT8 dbSysConfig; - UINT32 abValue; - UINT8 dbValue; - UINT8 dbEfuse; - UINT8 dbCg2WR; - UINT8 dbCg1Pll; - UINT8 cimNbSbGen2; - UINT8 cimSpiFastReadEnable; - UINT8 cimSpiFastReadSpeed; - UINT8 cimSioHwmPortEnable; - UINT8 SataPortNum; - - cimNbSbGen2 = pConfig->NbSbGen2; -// Adding Fast Read Function support - if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) { - cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; - } else { - cimSpiFastReadEnable = cimSpiFastReadEnableDefault; - } - cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; - cimSioHwmPortEnable = pConfig->SioHwmPortEnable; -#if SB_CIMx_PARAMETER == 0 - cimNbSbGen2 = cimNbSbGen2Default; - cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); - cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault)); - cimSpiFastReadEnable = cimSpiFastReadEnableDefault; - cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; - cimSioHwmPortEnable = cimSioHwmPortEnableDefault; -#endif - -// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct - RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0); - -// Set A-Link bridge access address. This address is set at device 14h, function 0, -// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary. - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); - writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction - abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation - abValue = abValue | BIT0; - writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue); - writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. - writeAlink (0x34, readAlink (0x34) | BIT9); - - dbEfuse = FUSE_ID_EFUSE_LOC; - getEfuseStatus (&dbEfuse); - if ( dbEfuse == M1_D1_FUSE_ID ) { - dbEfuse = MINOR_ID_EFUSE_LOC; - getEfuseStatus (&dbEfuse); - if ( dbEfuse == M1_MINOR_ID ) { - // Limit ALink speed to 2.5G if Hudson-M1 - cimNbSbGen2 = 0; - } - } -// Step 1: -// AXINDP_Reg 0xA4[0] = 0x1 -// Step 2: -// AXCFG_Reg 0x88[3:0] = 0x2 -// Step3: -// AXINDP_Reg 0xA4[18] = 0x1 - if ( cimNbSbGen2 == TRUE ) { - rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0); - rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2); - rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18); - } - -// Set Build option into SB - WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); - if (cimSioHwmPortEnable) { - // Use Wide IO Port 1 to provide access to the superio HWM registers. - WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress)); - RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable - RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes - } - RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); - RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); -// Enabled SMBUS0/SMBUS1 (ASF) Base Address - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1] - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr)); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase)); - - dbEfuse = SATA_FIS_BASE_EFUSE_LOC; - getEfuseStatus (&dbEfuse); - - programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0])); - - - SataPortNum = 0; - for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) { - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum); - SbStall (2); - RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00); - SbStall (2); - } - - - //The following bits must be set before enabling SPI prefetch. - // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0). - // if Ec is enable - // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed. - // else - // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at - // the speed. - getChipSysMode (&dbSysConfig); - if (pConfig->BuildParameters.SpiSpeed < 0x02) { - pConfig->BuildParameters.SpiSpeed = 0x01; - if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02; - } - - if (pConfig->SbSpiSpeedSupport) { - RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26)); - RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 ); - RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12)); - } - // SPI Fast Read Function - if ( cimSpiFastReadEnable ) { - RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18); - } else { - RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00); - } - - if ( cimSpiFastReadSpeed ) { - RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14)); - } - //Program power on pci init table - programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) ); - - programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); - - dbValue = 0x0A; - WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); - ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); - dbValue &= 0xEF; - WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); - -// Change the CG PLL multiplier to x1.1 - if ( pConfig->UsbRxMode !=0 ) { - dbCg2WR = 0x00; - dbCg1Pll = 0x3A; - ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A); - ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll); - dbCg2WR &= BIT4; - if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 )) - { - RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10); - dbValue = 0x06; - WriteIO (0xCF9, AccWidthUint8, &dbValue); - } else { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00); - } - } - - RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0); - - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD ); - - if (dbEfuse & BIT0) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04); - } - - ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus); - if ( ((dbPortStatus & 0xF0) == 0x10) ) { - RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5); - } - - if ( pConfig->BuildParameters.LegacyFree ) { - RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); - } else { - RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); - } - - dbValue = 0x09; - WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); - ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); - if ( !pConfig->BuildParameters.EcKbd ) { - // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input - dbValue = dbValue & 0xF9; - } - if ( pConfig->BuildParameters.LegacyFree ) { - // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. - dbValue = dbValue & 0x9F; - } - // Enabled IRQ input - dbValue = dbValue | BIT4; - WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); - -#ifndef NO_EC_SUPPORT - getChipSysMode (&dbPortStatus); - if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) { - // EC is disabled by jumper setting or board config - RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0); - } else { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08); - ecPowerOnInit ( pConfig); - } -#endif - - ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue); - if (dbValue & ChipSysIntClkGen) { - ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue); - if (dbValue & BIT2) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20); - } else { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00); - } - } - - // Restore GPP clock to on as it may be off during last POST when some device was disabled; - // the device can't be detected if enabled again as the values retain on S5 and warm reset. - RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF); - RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF); - - // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5); -} diff --git a/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h b/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h deleted file mode 100644 index 6b8c8d40ec..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h +++ /dev/null @@ -1,523 +0,0 @@ -/** - * @file - * - * Southbridge CIMx Function Support Define (All) - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -// Southbridge SBMAIN Routines - -/** - * Southbridge Main Function Public Function - * - */ - -/** - * sbBeforePciInit - Config Southbridge before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbBeforePciInit (IN AMDSBCFG* pConfig); - - -/** - * sbAfterPciInit - Config Southbridge after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbAfterPciInit (IN AMDSBCFG* pConfig); - -/** - * sbMidPostInit - Config Southbridge during middle of POST - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbMidPostInit (IN AMDSBCFG* pConfig); - -/** - * sbLatePost - Prepare Southbridge to boot to OS. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbLatePost (IN AMDSBCFG* pConfig); - -/** - * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbBeforePciRestoreInit (IN AMDSBCFG* pConfig); - -/** - * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbAfterPciRestoreInit (IN AMDSBCFG* pConfig); - -/** - * sbSmmAcpiOn - Config Southbridge during ACPI_ON - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbSmmAcpiOn (IN AMDSBCFG* pConfig); - -/** - * CallBackToOEM - Call Back routine. - * - * - * - * @param[in] Func Callback ID. - * @param[in] Data Callback specific data. - * @param[in] pConfig Southbridge configuration structure pointer. - */ -unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig); - - -// Southbridge SBPOR Routines - -/** - * Southbridge power-on initial Public Function - * - */ - -/** - * sbPowerOnInit - Config Southbridge during power on stage. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbPowerOnInit (IN AMDSBCFG* pConfig); - - -// Southbridge Common Routines - -/** - * Southbridge Common Public Function - * - */ - -/** - * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. - * - * This settings should be done during S3 resume also - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void commonInitEarlyBoot (IN AMDSBCFG* pConfig); - -/** - * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB. - * - * This settings might not program during S3 resume - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void commonInitEarlyPost (IN AMDSBCFG* pConfig); - -/** - * commonInitLateBoot - Prepare Southbridge register setting to boot to OS. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void commonInitLateBoot (IN AMDSBCFG* pConfig); - -/** - * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig); - -void usbSetPllDuringS3 (IN AMDSBCFG* pConfig); -void usbDesertPll (IN AMDSBCFG* pConfig); - -/** - * hpetInit - Program Southbridge HPET function - * - * ** Eric - * - * @param[in] pConfig Southbridge configuration structure pointer. - * @param[in] pStaticOptions Platform build configuration table. - * - */ -void hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions); - -/** - * c3PopupSetting - Program Southbridge C state function - * - * ** Eric - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void c3PopupSetting (IN AMDSBCFG* pConfig); - -/** - * FusionRelatedSetting - Program Fusion C related function - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void FusionRelatedSetting (IN AMDSBCFG* pConfig); - -/** - * Southbridge Common Private Function - * - */ - -/** - * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig); - -// Southbridge SATA Routines - -/** - * Southbridge SATA Controller Public Function - * - */ - -/** - * sataInitMidPost - Config SATA controller in Middle POST. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sataInitMidPost (IN AMDSBCFG* pConfig); - -/** - * sataInitAfterPciEnum - Config SATA controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sataInitAfterPciEnum (IN AMDSBCFG* pConfig); - -/** - * sataInitBeforePciEnum - Config SATA controller before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sataInitBeforePciEnum (IN AMDSBCFG* pConfig); - -/** - * sataInitLatePost - Prepare SATA controller to boot to OS. - * - * - Set class ID to AHCI (if set to AHCI * Mode) - * - Enable AHCI interrupt - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sataInitLatePost (IN AMDSBCFG* pConfig); - -// Southbridge GEC Routines - -/** - * Southbridge GEC Controller Public Function - * - */ - -/** - * gecInitBeforePciEnum - Config GEC controller before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void gecInitBeforePciEnum (IN AMDSBCFG* pConfig); - -/** - * gecInitAfterPciEnum - Config GEC controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void gecInitAfterPciEnum (IN AMDSBCFG* pConfig); - -/** - * gecInitLatePost - Prepare GEC controller to boot to OS. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void gecInitLatePost (IN AMDSBCFG* pConfig); - -// Southbridge USB Routines - -/** - * Southbridge USB Controller Public Function - * - */ - -/** - * Config USB controller before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void usbInitBeforePciEnum (IN AMDSBCFG* pConfig); - -/** - * Config USB controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void usbInitAfterPciInit (IN AMDSBCFG* pConfig); - -/** - * Config USB1 EHCI controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig); -void usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig); -void usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig); -void usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig); -void usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig); -void usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig); -void usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig); - -// Southbridge SMI Service Routines (SMM.C) - -/** - * Southbridge SMI Service Routines Public Function - * - */ - -/** - * Southbridge SMI service module - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbSmmService (IN AMDSBCFG* pConfig); - -/** - * softwareSMIservice - Software SMI service - * - * ** Eric - * - * @param[in] void Southbridge software SMI service ID. - * - */ -void softwareSMIservice (IN void); - -// Southbridge GPP Controller Routines - -/** - * Southbridge GPP Controller Routines Public Function - * - */ - -/** - * GPP early programming and link training. On exit all populated EPs should be fully operational. - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbPcieGppEarlyInit (IN AMDSBCFG* pConfig); - -/** - * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void sbPcieGppLateInit (IN AMDSBCFG* pConfig); - -// Southbridge HD Controller Routines (AZALIA.C) - -/** - * Southbridge HD Controller Routines (AZALIA.C) Public Function - * - */ - -/** - * Config HD Audio Before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig); - -/** - * Config HD Audio after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -void azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig); - - -// Southbridge EC Routines - -#ifndef NO_EC_SUPPORT -/** - * Southbridge EC Controller Public Function - * - */ - -/** - * Config EC controller during power-on - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - void ecPowerOnInit (IN AMDSBCFG* pConfig); - -/** - * Config EC controller before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - void ecInitBeforePciEnum (IN AMDSBCFG* pConfig); - -/** - * Prepare EC controller to boot to OS. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - void ecInitLatePost (IN AMDSBCFG* pConfig); - -/** - * validateImcFirmware - Validate IMC Firmware. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - * @retval TRUE Pass - * @retval FALSE Failed - */ - unsigned char validateImcFirmware (IN AMDSBCFG* pConfig); - -/** - * validateImcFirmware - Validate IMC Firmware. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - void softwareToggleImcStrapping (IN AMDSBCFG* pConfig); -#endif - -#ifndef NO_HWM_SUPPORT -/** - * validateImcFirmware - Validate IMC Firmware. - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ - void hwmInit (IN AMDSBCFG* pConfig); -#endif - diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h deleted file mode 100644 index 2fa79238c1..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ /dev/null @@ -1,1135 +0,0 @@ - -/** - * @file - * - * Southbridge CIMx configuration structure define - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#ifndef _AMD_SBTYPE_H_ -#define _AMD_SBTYPE_H_ - -#pragma pack (push, 1) - -/** - * Entry point of Southbridge CIMx - * - * - * @param[in] Param1 Southbridge CIMx Function ID. - * @param[in] Param2 Southbridge Input Data. - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -typedef unsigned int (*SBCIM_HOOK_ENTRY) (unsigned int Param1, unsigned int Param2, void* pConfig); -/** - * SMM_SERVICE_ROUTINE - Southbridge SMI service routine - * - */ -typedef void (*SMM_SERVICE_ROUTINE) (void); - - -/** - * The STATIC platform information for CIMx Module. - * - */ -typedef struct _BUILDPARAM { - unsigned int BiosSize:3; /**< BiosSize - * @par - * BIOSSize [2.0] - BIOS Image Size - * @li <b>0</b> - 1M - * @li <b>1</b> - 2M - * @li <b>3</b> - 4M - * @li <b>7</b> - 8M - * In SB800, default ROM size is 1M Bytes, if your platform ROM bigger then 1M - * you have to set the ROM size outside CIMx module and before AGESA module get call - * - */ - unsigned int LegacyFree:1; /**< LegacyFree - * @par - * Config Southbridge CIMx module for Legacy Free Mode - */ - unsigned int SpiSpeed:2; /**< SpiSpeed - * @par - * SPI Speed [1.0] - the clock speed for non-fast read command - * @li <b>00</b> - 66Mhz - * @li <b>01</b> - 33Mhz - * @li <b>10</b> - 22Mhz - * @li <b>11</b> - 16.5Mhz - * - */ - unsigned int ImcEnableOverWrite:2; /**< ImcEnableOverWrite - * @par - * Imc Enable OverWrite - * @li <b>00</b> - by default strapping - * @li <b>01</b> - On - * @li <b>10</b> - Off - * - */ - unsigned int SpiFastReadEnable:1; /**< SpiFastReadEnable - * @par - * @li <b>00</b> - Disable SPI Fast Read Function - * @li <b>01</b> - Enable SPI Fast Read Function - */ - unsigned int SpiFastReadSpeed:2; /**< SpiFastReadSpeed - * @par - * @li <b>00</b> - 66Mhz - * @li <b>01</b> - 33Mhz - * @li <b>10</b> - 22Mhz - * @li <b>11</b> - 16.5Mhz - */ - unsigned int SpreadSpectrumType:1; /**< SpreadSpectrumType - * @par - * @li <b>0</b> - Spread Spectrum for normal platform - * @li <b>1</b> - Spread Spectrum for Ontario platform - */ -/** Dummy0 - Reserved */ - unsigned int Dummy0:4; - unsigned int EcKbd:1; /**< EcKbd - * @par - * EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse - * @li <b>0</b> - Use SIO PS/2 function. - * @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. ** - * @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system. - */ -/** EcChannel0 - Reserved */ - unsigned int EcChannel0:1; -/** UsbMsi - Reserved */ - unsigned int UsbMsi:1; -/** HdAudioMsi - Reserved */ - unsigned int HdAudioMsi:1; -/** LpcMsi - Reserved */ - unsigned int LpcMsi:1; -/** PcibMsi - Reserved */ - unsigned int PcibMsi:1; -/** AbMsi - Reserved */ - unsigned int AbMsi:1; -/** Dummy1 - Reserved */ - unsigned int Dummy1:9; - - unsigned int Smbus0BaseAddress; /**< Smbus0BaseAddress - * @par - * Smbus BASE Address - */ - unsigned int Smbus1BaseAddress; /**< Smbus1BaseAddress - * @par - * Smbus1 (ASF) BASE Address - */ - unsigned int SioPmeBaseAddress; /**< SioPmeBaseAddress - * @par - * SIO PME BASE Address - */ - unsigned int SioHwmBaseAddress; /**< SioHwmBaseAddress - * @par - * SIO HWM BASE Address - */ - unsigned int WatchDogTimerBase; /**< WatchDogTimerBase - * @par - * Watch Dog Timer Address - */ - unsigned int GecShadowRomBase; /**< GecShadowRomBase - * @par - * GEC (NIC) SHADOWROM BASE Address - */ - unsigned int SpiRomBaseAddress; /**< SpiRomBaseAddress - * @par - * SPI ROM BASE Address - */ - unsigned short AcpiPm1EvtBlkAddr; /**< AcpiPm1EvtBlkAddr - * @par - * ACPI PM1 event block Address - */ - unsigned short AcpiPm1CntBlkAddr; /**< AcpiPm1CntBlkAddr - * @par - * ACPI PM1 Control block Address - */ - unsigned short AcpiPmTmrBlkAddr; /**< AcpiPmTmrBlkAddr - * @par - * ACPI PM timer block Address - */ - unsigned short CpuControlBlkAddr; /**< CpuControlBlkAddr - * @par - * ACPI CPU control block Address - */ - unsigned short AcpiGpe0BlkAddr; /**< AcpiGpe0BlkAddr - * @par - * ACPI GPE0 block Address - */ - unsigned short SmiCmdPortAddr; /**< SmiCmdPortAddr - * @par - * SMI command port Address - */ - unsigned short AcpiPmaCntBlkAddr; /**< AcpiPmaCntBlkAddr - * @par - * ACPI PMA Control block Address - */ - unsigned int HpetBase; /**< HpetBase - * @par - * HPET Base address - */ - unsigned int SataIDESsid; /**< SataIDESsid - * @par - * SATA IDE mode SSID - */ - unsigned int SataRAIDSsid; /**< SataRAIDSsid - * @par - * SATA RAID mode SSID - */ - unsigned int SataRAID5Ssid; /**< SataRAID5Ssid - * @par - * SATA RAID5 mode SSID - */ - unsigned int SataAHCISsid; /**< SataAHCISsid - * @par - * SATA AHCI mode SSID - */ - unsigned int OhciSsid; /**< OhciSsid - * @par - * OHCI Controller SSID - */ - unsigned int EhciSsid; /**< EhciSsid - * @par - * EHCI Controller SSID - */ - unsigned int Ohci4Ssid; /**< Ohci4Ssid - * @par - * OHCI4 Controller SSID (Force USB 1.1 mode) - */ - unsigned int SmbusSsid; /**< SmbusSsid - * @par - * SMBUS controller SSID - */ - unsigned int IdeSsid; /**< IdeSsid - * @par - * IDE (Sata) controller SSID - */ - unsigned int AzaliaSsid; /**< AzaliaSsid - * @par - * HD Audio controller SSID - */ - unsigned int LpcSsid; /**< LpcSsid - * @par - * LPC controller SSID - */ - unsigned int PCIBSsid; /**< PCIBSsid - * @par - * PCIB controller SSID - */ -} BUILDPARAM; - -/** - * The EC fan MSGREG struct for CIMx Module. * - */ -typedef struct _EC_struct { - unsigned char MSGFun81zone0MSGREG0; ///<Thermal zone - unsigned char MSGFun81zone0MSGREG1; ///<Thermal zone - unsigned char MSGFun81zone0MSGREG2; ///<Thermal zone control byte 1 - unsigned char MSGFun81zone0MSGREG3; ///<Thermal zone control byte 2 - unsigned char MSGFun81zone0MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. - unsigned char MSGFun81zone0MSGREG5; ///<Hysteresis inforamtion - unsigned char MSGFun81zone0MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 - unsigned char MSGFun81zone0MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. - unsigned char MSGFun81zone0MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry - unsigned char MSGFun81zone0MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry - - //EC LDN9 funtion 81 zone 1 - unsigned char MSGFun81zone1MSGREG0; ///<Thermal zone - unsigned char MSGFun81zone1MSGREG1; ///<Thermal zone - unsigned char MSGFun81zone1MSGREG2; ///<Thermal zone control byte 1 - unsigned char MSGFun81zone1MSGREG3; ///<Thermal zone control byte 2 - unsigned char MSGFun81zone1MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. - unsigned char MSGFun81zone1MSGREG5; ///<Hysteresis inforamtion - unsigned char MSGFun81zone1MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 - unsigned char MSGFun81zone1MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. - unsigned char MSGFun81zone1MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry - unsigned char MSGFun81zone1MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry - - //EC LDN9 funtion 81 zone 2 - unsigned char MSGFun81zone2MSGREG0; ///<Thermal zone - unsigned char MSGFun81zone2MSGREG1; ///<Thermal zone - unsigned char MSGFun81zone2MSGREG2; ///<Thermal zone control byte 1 - unsigned char MSGFun81zone2MSGREG3; ///<Thermal zone control byte 2 - unsigned char MSGFun81zone2MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. - unsigned char MSGFun81zone2MSGREG5; ///<Hysteresis inforamtion - unsigned char MSGFun81zone2MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 - unsigned char MSGFun81zone2MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. - unsigned char MSGFun81zone2MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry - unsigned char MSGFun81zone2MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry - - //EC LDN9 funtion 81 zone 3 - unsigned char MSGFun81zone3MSGREG0; ///<Thermal zone - unsigned char MSGFun81zone3MSGREG1; ///<Thermal zone - unsigned char MSGFun81zone3MSGREG2; ///<Thermal zone control byte 1 - unsigned char MSGFun81zone3MSGREG3; ///<Thermal zone control byte 2 - unsigned char MSGFun81zone3MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. - unsigned char MSGFun81zone3MSGREG5; ///<Hysteresis inforamtion - unsigned char MSGFun81zone3MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 - unsigned char MSGFun81zone3MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. - unsigned char MSGFun81zone3MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry - unsigned char MSGFun81zone3MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry - - //EC LDN9 funtion 83 zone 0 - unsigned char MSGFun83zone0MSGREG0; ///<Thermal zone - unsigned char MSGFun83zone0MSGREG1; ///<Thermal zone - unsigned char MSGFun83zone0MSGREG2; ///<_AC0 - unsigned char MSGFun83zone0MSGREG3; ///<_AC1 - unsigned char MSGFun83zone0MSGREG4; ///<_AC2 - unsigned char MSGFun83zone0MSGREG5; ///<_AC3 - unsigned char MSGFun83zone0MSGREG6; ///<_AC4 - unsigned char MSGFun83zone0MSGREG7; ///<_AC5 - unsigned char MSGFun83zone0MSGREG8; ///<_AC6 - unsigned char MSGFun83zone0MSGREG9; ///<_AC7 - unsigned char MSGFun83zone0MSGREGA; ///<_CRT - unsigned char MSGFun83zone0MSGREGB; ///<_PSV - - //EC LDN9 funtion 83 zone 1 - unsigned char MSGFun83zone1MSGREG0; ///<Thermal zone - unsigned char MSGFun83zone1MSGREG1; ///<Thermal zone - unsigned char MSGFun83zone1MSGREG2; ///<_AC0 - unsigned char MSGFun83zone1MSGREG3; ///<_AC1 - unsigned char MSGFun83zone1MSGREG4; ///<_AC2 - unsigned char MSGFun83zone1MSGREG5; ///<_AC3 - unsigned char MSGFun83zone1MSGREG6; ///<_AC4 - unsigned char MSGFun83zone1MSGREG7; ///<_AC5 - unsigned char MSGFun83zone1MSGREG8; ///<_AC6 - unsigned char MSGFun83zone1MSGREG9; ///<_AC7 - unsigned char MSGFun83zone1MSGREGA; ///<_CRT - unsigned char MSGFun83zone1MSGREGB; ///<_PSV - - //EC LDN9 funtion 83 zone 2 - unsigned char MSGFun83zone2MSGREG0; ///<Thermal zone - unsigned char MSGFun83zone2MSGREG1; ///<Thermal zone - unsigned char MSGFun83zone2MSGREG2; ///<_AC0 - unsigned char MSGFun83zone2MSGREG3; ///<_AC1 - unsigned char MSGFun83zone2MSGREG4; ///<_AC2 - unsigned char MSGFun83zone2MSGREG5; ///<_AC3 - unsigned char MSGFun83zone2MSGREG6; ///<_AC4 - unsigned char MSGFun83zone2MSGREG7; ///<_AC5 - unsigned char MSGFun83zone2MSGREG8; ///<_AC6 - unsigned char MSGFun83zone2MSGREG9; ///<_AC7 - unsigned char MSGFun83zone2MSGREGA; ///<_CRT - unsigned char MSGFun83zone2MSGREGB; ///<_PSV - - //EC LDN9 funtion 83 zone 3 - unsigned char MSGFun83zone3MSGREG0; ///<Thermal zone - unsigned char MSGFun83zone3MSGREG1; ///<Thermal zone - unsigned char MSGFun83zone3MSGREG2; ///<_AC0 - unsigned char MSGFun83zone3MSGREG3; ///<_AC1 - unsigned char MSGFun83zone3MSGREG4; ///<_AC2 - unsigned char MSGFun83zone3MSGREG5; ///<_AC3 - unsigned char MSGFun83zone3MSGREG6; ///<_AC4 - unsigned char MSGFun83zone3MSGREG7; ///<_AC5 - unsigned char MSGFun83zone3MSGREG8; ///<_AC6 - unsigned char MSGFun83zone3MSGREG9; ///<_AC7 - unsigned char MSGFun83zone3MSGREGA; ///<_CRT - unsigned char MSGFun83zone3MSGREGB; ///<_PSV - - //EC LDN9 funtion 85 zone 0 - unsigned char MSGFun85zone0MSGREG0; ///<Thermal zone - unsigned char MSGFun85zone0MSGREG1; ///<Thermal zone - unsigned char MSGFun85zone0MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone0MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone0MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone0MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone0MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone0MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone0MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone0MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) - - //EC LDN9 funtion 85 zone 1 - unsigned char MSGFun85zone1MSGREG0; ///<Thermal zone - unsigned char MSGFun85zone1MSGREG1; ///<Thermal zone - unsigned char MSGFun85zone1MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone1MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone1MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone1MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone1MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone1MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone1MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone1MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) - - //EC LDN9 funtion 85 zone 2 - unsigned char MSGFun85zone2MSGREG0; ///<Thermal zone - unsigned char MSGFun85zone2MSGREG1; ///<Thermal zone - unsigned char MSGFun85zone2MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone2MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone2MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone2MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone2MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone2MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone2MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone2MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) - - //EC LDN9 funtion 85 zone 3 - unsigned char MSGFun85zone3MSGREG0; ///<Thermal zone - unsigned char MSGFun85zone3MSGREG1; ///<Thermal zone - unsigned char MSGFun85zone3MSGREG2; ///<AL0 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone3MSGREG3; ///<AL1 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone3MSGREG4; ///<AL2 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone3MSGREG5; ///<AL3 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone3MSGREG6; ///<AL4 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone3MSGREG7; ///<AL5 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone3MSGREG8; ///<AL6 PWM level in percentage (0 - 100%) - unsigned char MSGFun85zone3MSGREG9; ///<AL7 PWM level in percentage (0 - 100%) - - //EC LDN9 funtion 89 TEMPIN channel 0 - unsigned char MSGFun89zone0MSGREG0; ///<Thermal zone - unsigned char MSGFun89zone0MSGREG1; ///<Thermal zone - unsigned char MSGFun89zone0MSGREG2; ///<At DWORD bit 0-7 - unsigned char MSGFun89zone0MSGREG3; ///<At DWORD bit 15-8 - unsigned char MSGFun89zone0MSGREG4; ///<At DWORD bit 23-16 - unsigned char MSGFun89zone0MSGREG5; ///<At DWORD bit 31-24 - unsigned char MSGFun89zone0MSGREG6; ///<Ct DWORD bit 0-7 - unsigned char MSGFun89zone0MSGREG7; ///<Ct DWORD bit 15-8 - unsigned char MSGFun89zone0MSGREG8; ///<Ct DWORD bit 23-16 - unsigned char MSGFun89zone0MSGREG9; ///<Ct DWORD bit 31-24 - unsigned char MSGFun89zone0MSGREGA; ///<Mode bit 0-7 - - //EC LDN9 funtion 89 TEMPIN channel 1 - unsigned char MSGFun89zone1MSGREG0; ///<Thermal zone - unsigned char MSGFun89zone1MSGREG1; ///<Thermal zone - unsigned char MSGFun89zone1MSGREG2; ///<At DWORD bit 0-7 - unsigned char MSGFun89zone1MSGREG3; ///<At DWORD bit 15-8 - unsigned char MSGFun89zone1MSGREG4; ///<At DWORD bit 23-16 - unsigned char MSGFun89zone1MSGREG5; ///<At DWORD bit 31-24 - unsigned char MSGFun89zone1MSGREG6; ///<Ct DWORD bit 0-7 - unsigned char MSGFun89zone1MSGREG7; ///<Ct DWORD bit 15-8 - unsigned char MSGFun89zone1MSGREG8; ///<Ct DWORD bit 23-16 - unsigned char MSGFun89zone1MSGREG9; ///<Ct DWORD bit 31-24 - unsigned char MSGFun89zone1MSGREGA; ///<Mode bit 0-7 - - //EC LDN9 funtion 89 TEMPIN channel 2 - unsigned char MSGFun89zone2MSGREG0; ///<Thermal zone - unsigned char MSGFun89zone2MSGREG1; ///<Thermal zone - unsigned char MSGFun89zone2MSGREG2; ///<At DWORD bit 0-7 - unsigned char MSGFun89zone2MSGREG3; ///<At DWORD bit 15-8 - unsigned char MSGFun89zone2MSGREG4; ///<At DWORD bit 23-16 - unsigned char MSGFun89zone2MSGREG5; ///<At DWORD bit 31-24 - unsigned char MSGFun89zone2MSGREG6; ///<Ct DWORD bit 0-7 - unsigned char MSGFun89zone2MSGREG7; ///<Ct DWORD bit 15-8 - unsigned char MSGFun89zone2MSGREG8; ///<Ct DWORD bit 23-16 - unsigned char MSGFun89zone2MSGREG9; ///<Ct DWORD bit 31-24 - unsigned char MSGFun89zone2MSGREGA; ///<Mode bit 0-7 - - //EC LDN9 funtion 89 TEMPIN channel 3 - unsigned char MSGFun89zone3MSGREG0; ///<Thermal zone - unsigned char MSGFun89zone3MSGREG1; ///<Thermal zone - unsigned char MSGFun89zone3MSGREG2; ///<At DWORD bit 0-7 - unsigned char MSGFun89zone3MSGREG3; ///<At DWORD bit 15-8 - unsigned char MSGFun89zone3MSGREG4; ///<At DWORD bit 23-16 - unsigned char MSGFun89zone3MSGREG5; ///<At DWORD bit 31-24 - unsigned char MSGFun89zone3MSGREG6; ///<Ct DWORD bit 0-7 - unsigned char MSGFun89zone3MSGREG7; ///<Ct DWORD bit 15-8 - unsigned char MSGFun89zone3MSGREG8; ///<Ct DWORD bit 23-16 - unsigned char MSGFun89zone3MSGREG9; ///<Ct DWORD bit 31-24 - unsigned char MSGFun89zone3MSGREGA; ///<Mode bit 0-7 - - // FLAG for Fun83/85/89 support - unsigned short IMCFUNSupportBitMap; /// Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3; -} EC_struct; -/** SBGPPPORTCONFIG - Southbridge GPP port config structure */ -typedef struct { - unsigned int PortPresent:1; /**< Port connection - * @par - * @li <b>0</b> - Port doesn't have slot. No need to train the link - * @li <b>1</b> - Port connection defined and needs to be trained - */ - unsigned int PortDetected:1; /**< Link training status - * @par - * @li <b>0</b> - EP not detected - * @li <b>1</b> - EP detected - */ - unsigned int PortIsGen2:2; /**< Port link speed configuration - * @par - * @li <b>00</b> - Auto - * @li <b>01</b> - Forced GEN1 - * @li <b>10</b> - Forced GEN2 - * @li <b>11</b> - Reserved - */ - - unsigned int PortHotPlug:1; /**< Support hot plug? - * @par - * @li <b>0</b> - No support - * @li <b>1</b> - support - */ -/** PortMisc - Reserved */ - unsigned int PortMisc:27; -} SBGPPPORTCONFIG; - -/** CODECENTRY - Southbridge HD Audio OEM Codec structure */ -typedef struct _CODECENTRY { -/** Nid - Reserved ?? */ - unsigned char Nid; -/** Byte40 - Reserved ?? */ - unsigned int Byte40; -} CODECENTRY; - -/** CODECTBLLIST - Southbridge HD Audio Codec table list */ -typedef struct _CODECTBLLIST { -/** CodecID - Codec ID */ - unsigned int CodecID; -/** CodecTablePtr - Codec table pointer */ - CODECENTRY* CodecTablePtr; -} CODECTBLLIST; - -/** Sata Controller structure */ -typedef struct _SATAST { - unsigned char SataController:1; /**< SataController - * @par - * Sata Controller - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned char SataIdeCombMdPriSecOpt:1; /**< SataIdeCombMdPriSecOpt - Reserved */ - unsigned char SataSetMaxGen2:1; /**< SataSetMaxGen2 - * @par - * Sata Controller Set to Max Gen2 mode - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned char SataIdeCombinedMode:1; /**< SataIdeCombinedMode - * @par - * Sata IDE Controller set to Combined Mode - * @li <b>0</b> - enable - * @li <b>1</b> - disable - */ -/** SATARefClkSel - Reserved */ - unsigned char SATARefClkSel:2; // 4:5 -/** SATARefDivSel - Reserved */ - unsigned char SATARefDivSel:2; // 6:7 -} SATAST; - -/** _USBST Controller structure - * - * Usb Ohci1 Contoller is defined at BIT0 - * - 0:disable 1:enable - * (Bus 0 Dev 18 Func0) * - * Usb Ehci1 Contoller is defined at BIT1 - * - 0:disable 1:enable - * (Bus 0 Dev 18 Func2) * - * Usb Ohci2 Contoller is defined at BIT2 - * - 0:disable 1:enable - * (Bus 0 Dev 19 Func0) * - * Usb Ehci2 Contoller is defined at BIT3 - * - 0:disable 1:enable - * (Bus 0 Dev 19 Func2) * - * Usb Ohci3 Contoller is defined at BIT4 - * - 0:disable 1:enable - * (Bus 0 Dev 22 Func0) * - * Usb Ehci3 Contoller is defined at BIT5 - * - 0:disable 1:enable - * (Bus 0 Dev 22 Func2) * - * Usb Ohci4 Contoller is defined at BIT6 - * - 0:disable 1:enable - * (Bus 0 Dev 20 Func5) * - */ -typedef struct _USBST { - unsigned char Ohci1:1; ///< Ohci0 controller - 0:disable, 1:enable - unsigned char Ehci1:1; ///< Ehci1 controller - 0:disable, 1:enable - unsigned char Ohci2:1; ///< Ohci2 controller - 0:disable, 1:enable - unsigned char Ehci2:1; ///< Ehci2 controller - 0:disable, 1:enable - unsigned char Ohci3:1; ///< Ohci3 controller - 0:disable, 1:enable - unsigned char Ehci3:1; ///< Ehci3 controller - 0:disable, 1:enable - unsigned char Ohci4:1; ///< Ohci4 controller - 0:disable, 1:enable - unsigned char UTemp:1; ///< Reserved -} USBST; - -/** - * _AZALIAPIN - HID Azalia or GPIO define structure. - * - */ -typedef struct _AZALIAPIN { - unsigned char AzaliaSdin0:2; /**< AzaliaSdin0 - * @par - * SDIN0 is defined at BIT0 & BIT1 - * @li <b>00</b> - GPIO PIN - * @li <b>10</b> - As a Azalia SDIN pin - */ - unsigned char AzaliaSdin1:2; /**< AzaliaSdin1 - * @par - * SDIN0 is defined at BIT2 & BIT3 - * @li <b>00</b> - GPIO PIN - * @li <b>10</b> - As a Azalia SDIN pin - */ - unsigned char AzaliaSdin2:2; /**< AzaliaSdin2 - * @par - * SDIN0 is defined at BIT4 & BIT5 - * @li <b>00</b> - GPIO PIN - * @li <b>10</b> - As a Azalia SDIN pin - */ - unsigned char AzaliaSdin3:2; /**< AzaliaSdin3 - * @par - * SDIN0 is defined at BIT6 & BIT7 - * @li <b>00</b> - GPIO PIN - * @li <b>10</b> - As a Azalia SDIN pin - */ -} AZALIAPIN; - -/** AMDSBCFG - Southbridge CIMx configuration structure (Main) */ -typedef struct _AMDSBCFG { -/** StdHeader - Standard header for all AGESA/CIMx services. */ - AMD_CONFIG_PARAMS StdHeader; - -/** BuildParameters - The STATIC platform information for CIMx Module. */ - BUILDPARAM BuildParameters; - //offset 90 bytes (32-121) - //MsgXchgBiosCimx //offset 4 bytes (122-125) - // SATA Configuration - - union /**< union - Reserved */ - { /**< SATAMODE - Sata Controller structure */ -/** SataModeReg - Reserved */ - unsigned char SataModeReg; -/** SataMode - Reserved */ - SATAST SataMode; - } SATAMODE; -/** S3Resume - Flag of ACPI S3 Resume. */ - unsigned char S3Resume:1; // 8 -/** RebootRequired - Flag of Reboot system is required. */ - unsigned char RebootRequired:1; // 9 -/** SbSpiSpeedSupport - Reserved */ - unsigned char SbSpiSpeedSupport:1; // 10 -/**< SpreadSpectrum - * @par - * Spread Spectrum function - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned char SpreadSpectrum:1; // 11 -/** NbSbGen2 - Reserved */ - unsigned char NbSbGen2:1; // 12 - unsigned char GppGen2:1; // 13 - unsigned char GppMemWrImprove:1; // 14 -/** MsgXchgBiosCimxReserved - Reserved */ - unsigned char MsgXchgBiosCimxReserved:1; // 15 (BB USED) -/**< SataClass - SATA Controller mode [16:18] - * @par - * @li <b>000</b> - Native IDE mode - * @li <b>001</b> - RAID mode - * @li <b>010</b> - AHCI mode - * @li <b>011</b> - Legacy IDE mode - * @li <b>100</b> - IDE->AHCI mode - * @li <b>101</b> - AHCI mode as 4394 ID (AMD driver) - * @li <b>110</b> - IDE->AHCI mode as 4394 ID (AMD driver) - */ - unsigned short SataClass:3; // 16:18 -/**< Sata IDE Controller mode - * @par - * @li <b>0</b> - Legacy IDE mode - * @li <b>1</b> - Native IDE mode - */ - unsigned short SataIdeMode:1; // 19 -/**< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:) - * @par - * @li <b> BIT0 </b> - PORT0 set as ESP port - * @li <b> BIT1 </b> - PORT1 set as ESP port - * @li <b> BIT2 </b> - PORT2 set as ESP port - * @li <b> BIT3 </b> - PORT3 set as ESP port - * @li <b> BIT4 </b> - PORT4 set as ESP port - * @li <b> BIT5 </b> - PORT5 set as ESP port - */ - unsigned short SataEspPort:6; // 20:25 -/** SataPortPower - Reserved */ - unsigned short SataPortPower:6; // 31:26 - - // SATA Debug Option //offset 4 bytes (126-129) - -/**< SataPortMode - Force Each PORT to GEN1/GEN2 mode - * @par - * @li <b> 0 </b> Auto for each PORTs - * @li <b> BIT0 = 1</b> - PORT0 set to GEN1 - * @li <b> BIT1 = 1</b> - PORT0 set to GEN2 - * @li <b> BIT2 = 1</b> - PORT1 set to GEN1 - * @li <b> BIT3 = 1</b> - PORT1 set to GEN2 - * @li <b> BIT4 = 1</b> - PORT2 set to GEN1 - * @li <b> BIT5 = 1</b> - PORT2 set to GEN2 - * @li <b> BIT6 = 1</b> - PORT3 set to GEN1 - * @li <b> BIT7 = 1</b> - PORT3 set to GEN2 - * @li <b> BIT8 = 1</b> - PORT4 set to GEN1 - * @li <b> BIT9 = 1</b> - PORT4 set to GEN2 - * @li <b> BIT10 = 1</b> - PORT5 set to GEN1 - * @li <b> BIT11 = 1</b> - PORT5 set to GEN2 - */ - unsigned int SataPortMode:12; //11:0 -/** SATAClkSelOpt - Reserved */ - unsigned int SATAClkSelOpt:4; // Removed from coding side -/** SataAggrLinkPmCap - Reserved */ - unsigned int SataAggrLinkPmCap:1; //16, 0:OFF 1:ON -/** SataPortMultCap - Reserved */ - unsigned int SataPortMultCap:1; //17, 0:OFF 1:ON -/** SataClkAutoOff - Reserved */ - unsigned int SataClkAutoOff:1; //18, AutoClockOff 0:Disabled, 1:Enabled -/** SataPscCap - Reserved */ - unsigned int SataPscCap:1; //19, 0:Enable PSC capability, 1:Disable PSC capability -/** BIOSOSHandoff - Reserved */ - unsigned int BIOSOSHandoff:1; //20 -/** SataFisBasedSwitching - Reserved */ - unsigned int SataFisBasedSwitching:1; //21 -/** SataCccSupport - Reserved */ - unsigned int SataCccSupport:1; //22 -/** SataSscCap - Reserved */ - unsigned int SataSscCap:1; //23, 0:Enable SSC capability, 1:Disable SSC capability -/** SataMsiCapability - Reserved */ - unsigned int SataMsiCapability:1; //24 0:Hidden 1:Visible. This feature is disabled per RPR, but remains the interface. -/** SataForceRaid - Reserved */ - unsigned int SataForceRaid:1; //25 0:No function 1:Force RAID -/** SataDebugDummy - Reserved */ - unsigned int SataDebugDummy:6; //31:26 -// -// USB Configuration //offset 4 bytes (130-133) -// - -/** USBDeviceConfig - USB Controller Configuration - * - * - Usb Ohci1 Contoller is defined at BIT0 - * - 0:disable 1:enable - * (Bus 0 Dev 18 Func0) * - * - Usb Ehci1 Contoller is defined at BIT1 - * - 0:disable 1:enable - * (Bus 0 Dev 18 Func2) * - * - Usb Ohci2 Contoller is defined at BIT2 - * - 0:disable 1:enable - * (Bus 0 Dev 19 Func0) * - * - Usb Ehci2 Contoller is defined at BIT3 - * - 0:disable 1:enable - * (Bus 0 Dev 19 Func2) * - * - Usb Ohci3 Contoller is defined at BIT4 - * - 0:disable 1:enable - * (Bus 0 Dev 22 Func0) * - * - Usb Ehci3 Contoller is defined at BIT5 - * - 0:disable 1:enable - * (Bus 0 Dev 22 Func2) * - * - Usb Ohci4 Contoller is defined at BIT6 - * - 0:disable 1:enable - * (Bus 0 Dev 20 Func5) * - */ - union /**< union - Reserved */ - { /**< USBMODE - USB Controller structure */ -/** SataModeReg - Reserved */ - unsigned char UsbModeReg; -/** SataMode - Reserved */ - USBST UsbMode; - } USBMODE; -/*! - */ - -/**< GecConfig - * @par - * InChip Gbit NIC - * @li <b>1</b> - disable - * @li <b>0</b> - enable - */ - unsigned char GecConfig:1; //8 - -/**< IrConfig - * @par - * Ir Controller setting - * @li <b>00 </b> - disable - * @li <b>01 </b> - Rx and Tx0 - * @li <b>10 </b> - Rx and Tx1 - * @li <b>11 </b> - Rx and both Tx0,Tx1 - */ - unsigned char IrConfig:2; //9:10 - -/** GecDummy - Reserved */ - unsigned char GecDummy:5; //15:11 - - //Azalia Configuration - -/**< AzaliaController - Azalia Controller Configuration - * @par - * Azalia Controller [0-1] - * @li <b>0</b> - Auto : Detect Azalia controller automatically. - * @li <b>1</b> - Diable : Disable Azalia controller. - * @li <b>2</b> - Enable : Enable Azalia controller. - */ - unsigned char AzaliaController:2; //17:16 -/**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration - * @par - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned char AzaliaPinCfg:1; //18 -/**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration - * @par - * Support Front Panel configuration - * @li <b>0</b> - Auto - * @li <b>1</b> - disable - * @li <b>2</b> - enable - */ - unsigned char AzaliaFrontPanel:2; //20:19 -/**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration - * @par - * Force Front Panel configuration - * @li <b>0</b> - Not Detected - * @li <b>1</b> - Detected - */ - unsigned char FrontPanelDetected:1; //21 -/**< AzaliaSnoop - Azalia Controller Snoop feature Configuration - * @par - * Azalia Controller Snoop feature Configuration - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned char AzaliaSnoop:1; //22 -/** AzaliaDummy - Reserved */ - unsigned char AzaliaDummy:1; //23 - - union - { -/**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration - * - * SDIN0 is defined at BIT0 & BIT1 - * - 00: GPIO PIN - * - 01: Reserved - * - 10: As a Azalia SDIN pin - * - * SDIN1 is defined at BIT2 & BIT3 - * * Config same as SDIN0 - * SDIN2 is defined at BIT4 & BIT5 - * * Config same as SDIN0 - * SDIN3 is defined at BIT6 & BIT7 - * * Config same as SDIN0 - */ - unsigned char AzaliaSdinPin; - AZALIAPIN AzaliaConfig; - } AZALIACONFIG; - -/** AZOEMTBL - Azalia Controller OEM Codec Table Pointer - * - */ - union - { - PLACEHOLDER PlaceHolder; - CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 4 bytes (134-137) - } AZOEMTBL; - -/** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer - * - */ - union - { - PLACEHOLDER PlaceHolder; - void* pAzaliaOemFpCodecTablePtr; //offset 4 bytes (138-141) - } AZOEMFPTBL; - - //Miscellaneous Configuration //offset 4 bytes (142-145) -/** AnyHT200MhzLink - Reserved */ - unsigned int AnyHT200MhzLink:1; //0 -/**< HpetTimer - South Bridge Hpet Timer Configuration - * @par - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned int HpetTimer:1; //1 -/**< PciClks - PCI Slot Clock Control - * @par - * PCI SLOT 0 define at BIT0 - * - 00: disable - * - 01: enable - * - * PCI SLOT 1 define at BIT1 - * * Config same as PCI SLOT0 - * PCI SLOT 2 define at BIT2 - * * Config same as PCI SLOT0 - * PCI SLOT 3 define at BIT3 - * * Config same as PCI SLOT0 - * PCI SLOT 4 define at BIT4 - * * Config same as PCI SLOT0 - */ - unsigned int PciClks:5; //2:6 -/** MiscReserved1 - Reserved */ - unsigned int MiscReserved1:4; //9:7, Reserved -/** MobilePowerSavings - Debug function Reserved */ - unsigned int MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform -/** MiscDummy1 - Debug function Reserved */ - unsigned int MiscDummy1:1; -/** NativePcieSupport - Debug function Reserved */ - unsigned int NativePcieSupport:1; //13, 0:Enable, 1:Disabled -/** FlashPinConfig - Debug function Reserved */ - unsigned int FlashPinConfig:1; //14, 0:desktop mode 1:mobile mode -/** UsbPhyPowerDown - Debug function Reserved */ - unsigned int UsbPhyPowerDown:1; //15 -/** PcibClkStopOverride - Debug function Reserved */ - unsigned int PcibClkStopOverride:10; //25:16 -/**< HpetMsiDis - South Bridge HPET MSI Configuration - * @par - * @li <b>1</b> - disable - * @li <b>0</b> - enable - */ - unsigned int HpetMsiDis:1; //26 -/**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood - * @par - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned int ResetCpuOnSyncFlood:1; //27 -/**< LdtStpDisable - LdtStp# output disable - * @par - * @li <b>0</b> - LdtStp# output enable - * @li <b>1</b> - LdtStp# output disable - */ - unsigned int LdtStpDisable:1; //28 -/**< MTC1e - Message Triggered C1e - * @par - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned int MTC1e:1; //29 -/** MiscDummy - Reserved */ - unsigned int MiscDummy:2; //31:30 - unsigned int SioHwmPortEnable:1; // Enable SuperIO HWM access via LPC - - //DebugOptions //offset 4 bytes (146-149) -/** PcibAutoClkCtrlLow - Debug function Reserved */ - unsigned int PcibAutoClkCtrlLow:16; -/** PcibAutoClkCtrlHigh - Debug function Reserved */ - unsigned int PcibAutoClkCtrlHigh:16; - -/**< OEMPROGTBL - ACPI MMIO register setting table OEM override - * @par - * OEM table for customer override ACPI MMIO register in their code. - */ - union - { - PLACEHOLDER OemProgrammingTablePtr; //offset 4 bytes (150-153) - void *OemProgrammingTablePtr_Ptr; - } OEMPROGTBL; - - //Gpp Configuration //offset 24 bytes total (154-177) - union { - unsigned int PORTCFG32; - SBGPPPORTCONFIG PortCfg; - } PORTCONFIG[MAX_GPP_PORTS]; //offset 16 bytes - - unsigned int GppLinkConfig; // GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0] - // 0000 - Port ABCD -> 4:0:0:0 - // 0001 - N/A - // 0010 - Port ABCD -> 2:2:0:0 - // 0011 - Port ABCD -> 2:1:1:0 - // 0100 - Port ABCD -> 1:1:1:1 - // - unsigned int GppFoundGfxDev:4; //3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected - unsigned int CoreGen2Enable:1; //4 - unsigned int GppFunctionEnable:1; //5 - unsigned int GppUnhidePorts:1; //6 - unsigned int AlinkPhyPllPowerDown:1; //7 - unsigned int GppConfigDummy1:2; //9:8 - unsigned int GppLaneReversal:1; //10 - unsigned int GppPhyPllPowerDown:1; //11 - unsigned int GppCompliance :1; //12 - unsigned int GppPortAspm:8; //20:13 ASPM state for GPP ports, 14:13 for port0, ..., 20:19 for port3 - // 00 - Disabled - // 01 - L0s - // 10 - L1 - // 11 - L0s + L1 - // - unsigned int GppConfigDummy:11; //31:21 - - //TempMMIO //offset 4 bytes (178-181) - unsigned int TempMMIO; - - // DebugOption2 - unsigned int GecPhyStatus:1; - unsigned int GecDebugOptionDummy:7; - unsigned int SBGecPwr:2; - unsigned int SBGecDebugBus:1; - unsigned int DebugOption2Dummy1:1; - unsigned int DebugOption2Dummy2:1; - unsigned int SbPcieOrderRule:1; - unsigned int SbUsbPll:1; - unsigned int AcDcMsg:1; - unsigned int TimerTickTrack:1; - unsigned int ClockInterruptTag:1; - unsigned int OhciTrafficHanding:1; - unsigned int EhciTrafficHanding:1; - unsigned int FusionMsgCMultiCore:1; - unsigned int FusionMsgCStage:1; -/**< UsbRxMode - CG PLL multiplier for USB Rx 1.1 mode - * @par - * @li <b>0</b> - disable - * @li <b>1</b> - enable - */ - unsigned int UsbRxMode:1; - unsigned int DebugOption2Dummy3:9; // - - union - { - PLACEHOLDER DynamicGecRomAddressPtr; //offset 4 bytes (182-185) - void *DynamicGecRomAddress_Ptr; - } DYNAMICGECROM; - EC_struct Pecstruct; -} AMDSBCFG; - -/** SMMSERVICESTRUC- Southbridge SMI service structure */ -typedef struct _SMMSERVICESTRUC { -/** enableRegNum - Reserved */ - unsigned char enableRegNum; -/** enableBit - Reserved */ - unsigned char enableBit; -/** statusRegNum - Reserved */ - unsigned char statusRegNum; -/** statusBit - Reserved */ - unsigned char statusBit; -/** *debugMessage- Reserved */ - signed char *debugMessage; -/** serviceRoutine - Reserved */ - SMM_SERVICE_ROUTINE serviceRoutine; -} SMMSERVICESTRUC; - -#ifndef _NB_REG8MASK_ - -/** - * - Byte Register R/W structure - * - */ - typedef struct _Reg8Mask { -/** bRegIndex - Reserved */ - unsigned char bRegIndex; -/** bANDMask - Reserved */ - unsigned char bANDMask; -/** bORMask - Reserved */ - unsigned char bORMask; - } REG8MASK; -#endif - -/** - * - SATA Phy setting structure - * - */ -typedef struct _SATAPHYSETTING { -/** wPhyCoreControl - Reserved */ - unsigned short wPhyCoreControl; -/** dwPhyFineTune - Reserved */ - unsigned int dwPhyFineTune; -} SATAPHYSETTING; - -/** - * _ABTblEntry - AB link register table R/W structure - * - */ -typedef struct _ABTblEntry { - /** regType : AB Register Type (ABCFG, AXCFG and so on) */ - unsigned char regType; - /** regIndex : AB Register Index */ - unsigned int regIndex; - /** regMask : AB Register Mask */ - unsigned int regMask; - /** regData : AB Register Data */ - unsigned int regData; -} ABTBLENTRY; - -/** - * _AcpiRegWrite - ACPI MMIO register R/W structure - * - */ -typedef struct _AcpiRegWrite { - /** MmioBase : Index of Soubridge block (For instence GPIO_BASE:0x01 SMI_BASE:0x02) */ - unsigned char MmioBase; - /** MmioReg : Register index */ - unsigned char MmioReg; - /** DataANDMask : AND Register Data */ - unsigned char DataANDMask; - /** DataOrMask : Or Register Data */ - unsigned char DataOrMask; -} AcpiRegWrite; - -/** - * PCI_ADDRESS - PCI access structure - * - */ -#define PCI_ADDRESS(bus, dev, func, reg) \ -(unsigned int) ( (((unsigned int)bus) << 24) + (((unsigned int)dev) << 19) + (((unsigned int)func) << 16) + ((unsigned int)reg) ) - -/** - * CIM_STATUS - CIMx module function return code - */ -typedef unsigned int CIM_STATUS; -/** - * CIM_SUCCESS - Executed without error - */ -#define CIM_SUCCESS 0x00000000 -/** - * CIM_ERROR - call error - */ -#define CIM_ERROR 0x80000000 -/** - * CIM_UNSUPPORTED - function does not support - */ -#define CIM_UNSUPPORTED 0x80000001 - -#pragma pack (pop) - -/** - * CIMX_OPTION_DISABLED - Define disable in module - */ -#define CIMX_OPTION_DISABLED 0 -/** - * CIMX_OPTION_ENABLED - Define enable in module - */ -#define CIMX_OPTION_ENABLED 1 - -/** - * SATA_IDE_COMBINE_ENABLE -Define Enable Combined Mode - */ -#define SATA_IDE_COMBINE_ENABLE 0 - -/** - * SATA_IDE_COMBINE_DISABLE -Define Disable Combined Mode - */ -#define SATA_IDE_COMBINE_DISABLE 1 - -// mov al, code -// out 80h, al -// jmp $ - -/** - * DBG_STOP - define a debug point - */ -#define DBG_STOP __asm _emit 0xEB __asm _emit 0xFE - -/** - * STOP_CODE - define a debug point - * Warning: AL gets destroyed! - */ -#define STOP_CODE (code) __asm __emit 0xB0 __asm __emit code __asm __emit 0xE6 \ - __asm __emit 0x80 __asm _emit 0xEB __asm _emit 0xFE - -#endif // _AMD_SBTYPE_H_ diff --git a/src/vendorcode/amd/cimx/sb800/SMM.c b/src/vendorcode/amd/cimx/sb800/SMM.c deleted file mode 100644 index 1d501e5b6f..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SMM.c +++ /dev/null @@ -1,79 +0,0 @@ -/** - * @file - * - * Southbridge SMM service function - * - * Prepare SMM service module for IBV call Southbridge SMI service routine. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -// -// Declaration of local functions -// - -/** - * Southbridge SMI service module - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -sbSmmService ( - IN AMDSBCFG* pConfig - ) -{ -} - -/** - * softwareSMIservice - Software SMI service - * - * @param[in] VOID Southbridge software SMI service ID. - * - */ -VOID -softwareSMIservice ( - IN VOID - ) -{ -} diff --git a/src/vendorcode/amd/cimx/sb800/SbModInf.c b/src/vendorcode/amd/cimx/sb800/SbModInf.c deleted file mode 100644 index 6ce0df9023..0000000000 --- a/src/vendorcode/amd/cimx/sb800/SbModInf.c +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file - * - * Function dispatcher. - * - * - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - - -/// module header -VOLATILE AMD_MODULE_HEADER mNbModuleHeader = { - 'DOM$', ///< Standard AMD module signature - CIMX_SB_ID, ///< Chipset ID - CIMX_SB_REVISION, ///< CIMx version - AmdSbDispatcher, ///< Pointer to the module entry - NULL ///< Pointer link to next module header -}; diff --git a/src/vendorcode/amd/cimx/sb800/USB.c b/src/vendorcode/amd/cimx/sb800/USB.c deleted file mode 100644 index 14794cd2bb..0000000000 --- a/src/vendorcode/amd/cimx/sb800/USB.c +++ /dev/null @@ -1,431 +0,0 @@ -/** - * @file - * - * Config Southbridge USB controller - * - * Init USB features. - * - * @xrefitem bom "File Content Label" "Release Content" - * @e project: CIMx-SB - * @e sub-project: - * @e \$Revision:$ @e \$Date:$ - * - */ -/* - ***************************************************************************** - * - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * *************************************************************************** - * - */ - - -#include "SBPLATFORM.h" -#include "cbtypes.h" - -// -// Declaration of local functions -// - -/** - * EhciInitAfterPciInit - Config USB controller after PCI emulation - * - * @param[in] Value Controller PCI config address (bus# + device# + function#) - * @param[in] pConfig Southbridge configuration structure pointer. - */ -VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig); -/** - * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation - * - * @param[in] Value Controller PCI config address (bus# + device# + function#) - * @param[in] pConfig Southbridge configuration structure pointer. - */ -VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig); - -/** - * SetEhciP11Wr - FIXME - * - * @param[in] Value Controller PCI config address (bus# + device# + function#) - * @param[in] pConfig Southbridge configuration structure pointer. - */ -UINT32 SetEhciPllWr (IN UINT32 Value, IN AMDSBCFG* pConfig); - - -/** - * usbInitBeforePciEnum - Config USB controller before PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usbInitBeforePciEnum ( - IN AMDSBCFG* pConfig - ) -{ - // Disabled All USB controller - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0); - // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST. - // Enable UsbResumeEnable (USB PME) * Default value - // In SB700 USB SleepCtrl set as BIT10+BIT9, but SB800 default is BIT9+BIT8 (6 uframes) - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, pConfig->USBMODE.UsbModeReg); -} - -/** - * usbInitAfterPciInit - Config USB controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usbInitAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT1, BIT1); - - usb1EhciInitAfterPciInit (pConfig); - usb2EhciInitAfterPciInit (pConfig); - usb3EhciInitAfterPciInit (pConfig); - usb1OhciInitAfterPciInit (pConfig); - usb2OhciInitAfterPciInit (pConfig); - usb3OhciInitAfterPciInit (pConfig); - usb4OhciInitAfterPciInit (pConfig); - - if ( pConfig->UsbPhyPowerDown ) { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0); - } else - { - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0); - } - -} - -/** - * usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usb1EhciInitAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddDeviceId; - ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16); - EhciInitAfterPciInit (ddDeviceId, pConfig); -} - -/** - * usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usb2EhciInitAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddDeviceId; - ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16); - EhciInitAfterPciInit (ddDeviceId, pConfig); -} - -/** - * usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usb3EhciInitAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddDeviceId; - ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16); - EhciInitAfterPciInit (ddDeviceId, pConfig); -} - -VOID -EhciInitAfterPciInit ( - IN UINT32 Value, - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddBarAddress; - UINT32 ddVar; - //Get BAR address - ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress); - if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) { - //Enable Memory access - RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1); - if (pConfig->BuildParameters.EhciSsid != 0 ) { - RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid); - } - //USB Common PHY CAL & Control Register setting - ddVar = 0x00020F00; - WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar); - // RPR IN AND OUT DATA PACKET FIFO THRESHOLD - // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40 - RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040); - // RPR EHCI Dynamic Clock Gating Feature - RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~BIT12, 0); - // RPR Enable adding extra flops to PHY rsync path - // Step 1: - // EHCI_BAR 0xB4 [6] = 1 - // EHCI_BAR 0xB4 [7] = 0 - // EHCI_BAR 0xB4 [12] = 0 ("VLoad") - // All other bit field untouched - // Step 2: - // EHCI_BAR 0xB4[12] = 1 - RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00); - RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12); - //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support - //RPR recommended setting "EHCI Async Park Mode" - //Set EHCI_pci_configx50[23]='0' to enable "EHCI Async Park Mode support" - //RPR Enabling EHCI Async Stop Enhancement - //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement - RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(BIT23), BIT29 + BIT23 + BIT8 + BIT6); - // RPR recommended setting "EHCI Advance PHY Power Savings" - // Set EHCI_pci_configx50[31]='1' - // Fix for EHCI controller driver yellow sign issue under device manager - // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1 - RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15); - // RPR USB Delay A-Link Express L1 State - // RPR PING Response Fix Enable EHCI_PCI_Config x54[1] = 1 - // RPR Empty-list Detection Fix Enable EHCI_PCI_Config x54[3] = 1 - RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, BIT0); - if ( pConfig->BuildParameters.UsbMsi) { - RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00); - } - } -} - -/** - * usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usb1OhciInitAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddDeviceId; - ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16); - OhciInitAfterPciInit (ddDeviceId, pConfig); -} - -/** - * usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usb2OhciInitAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddDeviceId; - ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16); - OhciInitAfterPciInit (ddDeviceId, pConfig); -} - -/** - * usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usb3OhciInitAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddDeviceId; - ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16); - OhciInitAfterPciInit (ddDeviceId, pConfig); -} - -/** - * usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation - * - * - * - * @param[in] pConfig Southbridge configuration structure pointer. - * - */ -VOID -usb4OhciInitAfterPciInit ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddDeviceId; - ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16); - OhciInitAfterPciInit (ddDeviceId, pConfig); - if (pConfig->BuildParameters.Ohci4Ssid != 0 ) { - RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid); - } -} - -VOID -OhciInitAfterPciInit ( - IN UINT32 Value, - IN AMDSBCFG* pConfig - ) -{ - // Disable the MSI capability of USB host controllers - RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); - RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT12), 0x00); - // RPR USB SMI Handshake - RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00); - // SB02186 - RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00); - if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) { - if ( pConfig->BuildParameters.OhciSsid != 0 ) { - RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid); - } - } - //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices - //OHCI 0_PCI_Config 0x50[30] = 1 - RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6); - if ( pConfig->BuildParameters.UsbMsi) { - RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00); - RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5); - } -} - - -UINT32 -SetEhciPllWr ( - IN UINT32 Value, - IN AMDSBCFG* pConfig - ) -{ - UINT32 ddRetureValue; - UINT32 ddBarAddress; - UINT16 dwVar; - UINT16 dwData; - UINT8 portSC; - ddRetureValue = 0; - dwData = 0; - // Memory, and etc. - //_asm { jmp $}; - RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00); - RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02); - // Get Bar address - ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress); - for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) { - // Get OHCI command registers - ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar); - if ( dwVar & BIT6 ) { - ddRetureValue = ddBarAddress + portSC; - RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0); - for (;;) { - SbStall (5); - ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData); - if (dwData == 0x1005) break; - } - dwData = 0; - } - } - return ddRetureValue; -} - -VOID -usbSetPllDuringS3 ( - IN AMDSBCFG* pConfig - ) -{ - UINT32 resumeEhciPortTmp; - UINT32 resumeEhciPort; - resumeEhciPortTmp = 0; - resumeEhciPort = 0; -// UINT32 ddDeviceId; -//if Force Port Resume == 1 -// { -// clear Force Port Resume; -// while (!(PORTSC == 0x1005)){wait 5 us; read PORTSC;} -// } - if (pConfig->USBMODE.UsbModeReg & BIT1) { - resumeEhciPortTmp = SetEhciPllWr (USB1_EHCI_BUS_DEV_FUN << 16, pConfig); - if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; - } - if (pConfig->USBMODE.UsbModeReg & BIT3) { - resumeEhciPortTmp = SetEhciPllWr (USB2_EHCI_BUS_DEV_FUN << 16, pConfig); - if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; - } - if (pConfig->USBMODE.UsbModeReg & BIT5) { - resumeEhciPortTmp = SetEhciPllWr (USB3_EHCI_BUS_DEV_FUN << 16, pConfig); - if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp; - } - - RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); - RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); - RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); - RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20); - SbStall (10); - RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00); - RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); - RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); - RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); - RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29); - - if (resumeEhciPort > 0) { - RWMEM (resumeEhciPort, AccWidthUint8, ~BIT7, BIT7); - SbStall (4000); - RWMEM (resumeEhciPort, AccWidthUint8, ~BIT6, BIT6); - } - - RWPCI ((UINT32) (USB1_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); - RWPCI ((UINT32) (USB2_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); - RWPCI ((UINT32) (USB3_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03); - -} - |