diff options
| author | Chris Wang <chris.wang@amd.corp-partner.google.com> | 2020-12-18 15:01:36 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-25 09:10:40 +0000 |
| commit | 027b8b2ab91284be3e593a7e2c0ffb8fb6d325f5 (patch) | |
| tree | 1f4b1c36935189993d775276ffa620d6c833d08a | |
| parent | 4e66d932c79fe32954319c233850e3ebf10df141 (diff) | |
mb/google/zork: add eDP tuning parameter to fix the eDP noise
needs to adjust the eDP phy setting to fix the eDP noise for WWAN.
DP_VS_LEVEL0_PREEMPH_LEVEL0, = 0x00 (0.4v 0db) swing 0, pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004B
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ibe720e26d2257e05a989eaa1fd85d542005cf6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48734
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/zork/variants/vilboz/overridetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index f484e9a713..ddcaf53d3b 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -23,6 +23,16 @@ chip soc/amd/picasso register "telemetry_vddcr_soc_slope_mA" = "20001" register "telemetry_vddcr_soc_offset" = "168" + # eDP phy tuning settings + register "dp_phy_override" = "ENABLE_EDP_TUNINGSET" + + register "edp_tuningset" = "{ + .dp_vs_pemph_level = 0x0, + .deemph_6db4 = 0x004b, + .boostadj = 0x0, + .margin_deemph = 0x80, + }" + # USB OC pin mapping register "usb_port_overcurrent_pin[1]" = "USB_OC_NONE" # LTE instead of USB C1 |