diff options
| author | Shelley Chen <shchen@google.com> | 2020-10-21 22:46:14 -0700 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2020-10-23 06:05:22 +0000 |
| commit | 0263e0ff65d50a616e1ae04ab0837c0d90118d19 (patch) | |
| tree | a1ce28d422fecc6198545ae056639f36eae58d6c | |
| parent | 3827f56fe1f97c4dc19af94782ed9cce89cec723 (diff) | |
sc7180: enable RECOVERY_MRC_CACHE
Enable caching of memory training data for recovery as well as normal
mode because memory training is taking too long in recovery as well.
This required creating a space in the fmap for RECOVERY_MRC_CACHE.
BUG=b:150502246
BRANCH=None
TEST=Run power_state:rec twice on lazor. Ensure that on first boot,
memory training occurs and on second boot, memory training is
skipped.
Change-Id: Id9059a8edd7527b0fe6cdc0447920d5ecbdf296e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46651
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/trogdor/chromeos.fmd | 5 | ||||
| -rw-r--r-- | src/soc/qualcomm/common/qclib.c | 26 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7180/Kconfig | 1 |
3 files changed, 10 insertions, 22 deletions
diff --git a/src/mainboard/google/trogdor/chromeos.fmd b/src/mainboard/google/trogdor/chromeos.fmd index d5324eee49..f6960761ef 100644 --- a/src/mainboard/google/trogdor/chromeos.fmd +++ b/src/mainboard/google/trogdor/chromeos.fmd @@ -14,7 +14,10 @@ FLASH@0x0 8M { RW_VPD(PRESERVE) 32K RW_NVRAM(PRESERVE) 16K - RW_MRC_CACHE(PRESERVE) 8K + UNIFIED_MRC_CACHE(PRESERVE) 16K { + RECOVERY_MRC_CACHE 8K + RW_MRC_CACHE 8K + } RW_ELOG(PRESERVE) 4K RW_SHARED 4K { SHARED_DATA diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index d4796a2e7c..93588904b5 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -74,14 +74,6 @@ static void write_table_entry(struct qclib_cb_if_table_entry *te) } else if (!strncmp(QCLIB_TE_DDR_TRAINING_DATA, te->name, sizeof(te->name))) { - /* - * Don't store training data if we're in recovery mode - * because we always want to retrain due to - * possibility of RW training data possibly being - * updated to a different format. - */ - if (vboot_recovery_mode_enabled()) - return; assert(!mrc_cache_stash_data(MRC_TRAINING_DATA, QCLIB_VERSION, (const void *)te->blob_address, te->size)); @@ -138,20 +130,12 @@ void qclib_load_and_run(void) /* output area, QCLib fills in DDR details */ qclib_add_if_table_entry(QCLIB_TE_DDR_INFORMATION, NULL, 0, 0); - /* - * We never want to use training data when booting into - * recovery mode. - */ - if (vboot_recovery_mode_enabled()) { + /* Attempt to load DDR Training Blob */ + data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION, + _ddr_training, REGION_SIZE(ddr_training)); + if (data_size < 0) { + printk(BIOS_ERR, "Unable to load previous training data.\n"); memset(_ddr_training, 0, REGION_SIZE(ddr_training)); - } else { - /* Attempt to load DDR Training Blob */ - data_size = mrc_cache_load_current(MRC_TRAINING_DATA, QCLIB_VERSION, - _ddr_training, REGION_SIZE(ddr_training)); - if (data_size < 0) { - printk(BIOS_ERR, "Unable to load previous training data.\n"); - memset(_ddr_training, 0, REGION_SIZE(ddr_training)); - } } qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, _ddr_training, REGION_SIZE(ddr_training), 0); diff --git a/src/soc/qualcomm/sc7180/Kconfig b/src/soc/qualcomm/sc7180/Kconfig index c37aff9db3..4cd1c41cac 100644 --- a/src/soc/qualcomm/sc7180/Kconfig +++ b/src/soc/qualcomm/sc7180/Kconfig @@ -19,6 +19,7 @@ config SOC_QUALCOMM_SC7180 select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select CACHE_MRC_SETTINGS + select HAS_RECOVERY_MRC_CACHE select COMPRESS_BOOTBLOCK if SOC_QUALCOMM_SC7180 |