diff options
| author | Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> | 2023-08-23 15:21:07 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-24 13:39:49 +0000 |
| commit | 00e92f45389e7086c6e357aba525e75d09363160 (patch) | |
| tree | cd6a02fb397be2ff3677703d7683c0a2418e3585 | |
| parent | d6c2e054f8ba6e0385e33f7ff295aba02efb2121 (diff) | |
mb/google/dedede/var/boxy: Enable 100M mode blink in RTL8111H LAN LED config
Enable bit 9 for 100M mode green LED blink.
Reference:
- RTL8111H-CG Datasheet 1.92 section 7.2 for customizable led configuration
BUG=b:293983804
TEST=emerge-dedede coreboot and verify LAN LED behavior
Change-Id: Ice5686affcc014a2dfd35b7f579c8eaa38c2d3fe
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
| -rw-r--r-- | src/mainboard/google/dedede/variants/boxy/overridetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/boxy/overridetree.cb b/src/mainboard/google/dedede/variants/boxy/overridetree.cb index fd6e992edd..2514efde68 100644 --- a/src/mainboard/google/dedede/variants/boxy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boxy/overridetree.cb @@ -222,7 +222,7 @@ chip soc/intel/jasperlake end # I2C 4 device pci 1c.2 on chip drivers/net - register "customized_leds" = "0x05af" + register "customized_leds" = "0x07af" register "wake" = "GPE0_DW0_03" # GPP_B3 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" register "device_index" = "0" |