diff options
| author | Reto Buerki <reet@codelabs.ch> | 2020-07-16 13:14:00 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-17 13:39:26 +0000 |
| commit | 00531f067c07a930b545e191dea567c6897783e2 (patch) | |
| tree | bdf5525bce205554b8ba3b6703d5cd8c36f79f8b | |
| parent | 93f2f0f7bd89fee693a79f68e5025af1cdc4f225 (diff) | |
mb/up/squared: Make mini PCIe port mode configurable
Add config choice menu and pad configuration to put Mini PCIe port into
mSATA mode.
The vendor firmware's "Chipset->Mini PCIe / mSATA Switch" option has
been used together with the output of inteltool and intel2pm to deduce
the exact pad configuration.
Note: the vendor firmware does not autodetect the mode, and the default
setting for the port is "Mini PCIe".
Tested with Kingston SUV500MS120G mSATA SSD.
Change-Id: Ic2da1dd4252ebb5e373bc65418e321f566d4c10f
Signed-off-by: Reto Buerki <reet@codelabs.ch>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/mainboard/up/squared/Kconfig | 18 | ||||
| -rw-r--r-- | src/mainboard/up/squared/gpio.h | 10 | ||||
| -rw-r--r-- | src/mainboard/up/squared/romstage.c | 2 |
3 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/up/squared/Kconfig b/src/mainboard/up/squared/Kconfig index ca8eef07b1..628b13e3aa 100644 --- a/src/mainboard/up/squared/Kconfig +++ b/src/mainboard/up/squared/Kconfig @@ -76,4 +76,22 @@ config CONSOLE_POST bool default y +choice + prompt "Mini PCIe port mode" + default MINI_PCIE_MODE_PCIE + help + Choose the operating mode of the mini PCIe port. + +config MINI_PCIE_MODE_PCIE + bool "PCIe" + help + Select this option to leave the mini PCIe port in PCIe mode. This is + also the default mode of the vendor firmware. + +config MINI_PCIE_MODE_MSATA + bool "mSATA" + help + Select this option to put the mini PCIe port into mSATA mode. +endchoice + endif diff --git a/src/mainboard/up/squared/gpio.h b/src/mainboard/up/squared/gpio.h index 1aecc189c1..876b32629d 100644 --- a/src/mainboard/up/squared/gpio.h +++ b/src/mainboard/up/squared/gpio.h @@ -777,4 +777,14 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), }; +/* + * Pad configuration to put MiniPCIe port into mSATA mode. + */ +static const struct pad_config msata_mode_gpio_table[] = { + /* ------- GPIO Group North-West ------- */ + + /* GPIO_213 - GPIO */ + PAD_CFG_TERM_GPO(GPIO_213, 0, UP_20K, DEEP), +}; + #endif /* CFG_GPIO_H */ diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 12e4135397..f4ccdafe51 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -103,6 +103,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) FSP_M_CONFIG *config = &memupd->FspmConfig; gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + if (CONFIG(MINI_PCIE_MODE_MSATA)) + gpio_configure_pads(msata_mode_gpio_table, ARRAY_SIZE(msata_mode_gpio_table)); uint8_t memory_skuid = get_memory_skuid(); printk(BIOS_DEBUG, "MAINBOARD: Found memory SKU ID: 0x%02x\n", memory_skuid); |