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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-06-28 19:07:33 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-06-29 04:10:15 +0200
commitefe2435fec15866d803579a2b84ec299e8b42fb5 (patch)
tree79b95cb0c1640f2079816fdbf641c5f78ffea440
parent9c41063713c64994083a4baddb22d41a685a95b8 (diff)
cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art
Embedding comments inside comments is illegal in the C specification, Clang enforces this. Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6154 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/cpu/amd/geode_gx2/cache_as_ram.inc19
1 files changed, 9 insertions, 10 deletions
diff --git a/src/cpu/amd/geode_gx2/cache_as_ram.inc b/src/cpu/amd/geode_gx2/cache_as_ram.inc
index 6a107fe5f1..45a04f8958 100644
--- a/src/cpu/amd/geode_gx2/cache_as_ram.inc
+++ b/src/cpu/amd/geode_gx2/cache_as_ram.inc
@@ -26,17 +26,17 @@
#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE)
#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
+
#include <cpu/amd/gx2def.h>
#include <cpu/x86/post_code.h>
-/***************************************************************************
-/**
-/** DCacheSetup
-/**
-/** Setup data cache for use as RAM for a stack.
-/**
-/** Max. size data cache =0x4000 (16KB)
-/**
-/***************************************************************************/
+
+/*
+ * DCacheSetup
+ *
+ * Setup data cache for use as RAM for a stack.
+ *
+ * Max. size data cache =0x4000 (16KB)
+ */
DCacheSetup:
/* Save the BIST result */
movl %eax, %ebx
@@ -201,4 +201,3 @@ __main:
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
-