diff options
| author | Zhao, Lijian <lijian.zhao@intel.com> | 2016-06-15 17:22:08 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-06-17 21:30:45 +0200 |
| commit | e813c15443c90ad09d9182f3cca94937df124847 (patch) | |
| tree | a6e8cd17e1df253da6abc57539d880ff1ff64d3c | |
| parent | fda691ef533bd2f0896c6cfe9e34440b9dc66f1b (diff) | |
google/reef: Update EMMC DLL setting in all mode
Update tuned DLL setting on all other mode, including SDR12
SDR25 and DDR50.
Change-Id: I1eb85ac6080fd78f63816d3fa9ef482484bd9f94
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/15210
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/google/reef/devicetree.cb | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index 9775dc80c8..e626a4c727 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -12,24 +12,24 @@ chip soc/intel/apollolake register "emmc_tx_data_cntl1" = "0x0C11" # HS400 required # EMMC TX DATA Delay 2# - # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 - # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 - # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 - # 0x00[6:0] stands for 0 delay for SDR12/Compatibility mode - register "emmc_tx_data_cntl2" = "0x1c1c1c00" + # 0x00[30:24] stands for 0*125 = no delay for SDR50 + # 0x2B[22:16] stands for 43*125 = 5375 pSec delay for DDR50 + # 0x29[14:8] stands for 41*125 = 5125 pSec delay for SDR25/HS50 + # 0x29[6:0] stands for 41*125 = 5125 pSec delay for SDR12 + register "emmc_tx_data_cntl2" = "0x002B2929" # EMMC RX CMD/DATA Delay 1# - # 0x1C[30:24] stands for 28*125 = 3500 pSec delay for SDR50 - # 0x1C[22:16] stands for 28*125 = 3500 pSec delay for DDR50 - # 0x1C[14:8] stands for 28*125 = 3500 pSec delay for SDR25/HS50 - # 0x00[6:0] stands for 0 delay for SDR12/Compatibility - register "emmc_rx_cmd_data_cntl1" = "0x1c1c1c00" + # 0x00[30:24] stands for 0*125 = no delay for SDR50 + # 0x12[22:16] stands for 18*125 = 2250 pSec delay for DDR50 + # 0x57[14:8] stands for 87*125 = 10875 pSec delay for SDR25/HS50 + # 0x3B[6:0] stands for 59*125= 7375 pSec delay for SDR12 + register "emmc_rx_cmd_data_cntl1" = "0x0012573B" # EMMC RX CMD/DATA Delay 2# # 0x01[17:16] stands for Rx Clock before Output Buffer # 0x00[14:8] stands for 0 delay for Auto Tuning Mode - # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for SDR104/HS200 - register "emmc_rx_cmd_data_cntl2" = "0x1001c" + # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 + register "emmc_rx_cmd_data_cntl2" = "0x1001C" device domain 0 on device pci 00.0 on end # - Host Bridge |