diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2020-10-20 20:53:27 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-26 06:43:38 +0000 |
| commit | e738a7e337a7446a7dee6e1ddb540c4fa4919a26 (patch) | |
| tree | 4a0d70ac4ea11659e2436d11cbd401755f25d085 | |
| parent | d3108d6c898e7789dc7e5c193158476bca7c4a6e (diff) | |
mb/google/volteer/var/terrador: Disable SRCCLKREQ1#
According to the schematic, SRCCLKREQ1# is not connected, so disable it
for terrador and todor.
BUG=b:171278849
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/volteer/variants/terrador/overridetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/google/volteer/variants/todor/overridetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 001d5f6835..ae26e79558 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -16,6 +16,9 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index 001d5f6835..ae26e79558 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -16,6 +16,9 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf |