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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-03-27 19:02:55 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-04-08 15:19:09 +0200
commite522258907c0f16fb46c8abfed64532fd3d81202 (patch)
tree9107ba99f00c4e3b5dde029326b1707de11829df
parente223c3aee9ac7f3b91fbbb810e9f2b2acd3fc4f6 (diff)
AGESA f14: Fix memory clock register decoding
Bottom five LSBs are used to store the running frequency of memory clock. Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19042 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
index ee14fed847..411caf843c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
@@ -528,7 +528,8 @@ MemMSetCSRNb (
IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: DIMM config changed\n");
RetVal = FALSE;
}
- if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr, NBPtr->DCTPtr->Timings.TargetSpeed) != ((Value & 7) + 1))) {
+ if (((Value & 0x4000) == 0) && (NBPtr->GetMemClkFreqId (NBPtr,
+ NBPtr->DCTPtr->Timings.TargetSpeed) != (Value & 0x1f))) {
IDS_HDT_CONSOLE (MEM_FLOW, "\tSTOP: MemClk has changed\n");
RetVal = FALSE;
}