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authorFelix Held <felix-coreboot@felixheld.de>2021-02-09 22:55:04 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-02-10 23:25:21 +0000
commite094b1f137fa6d3168b836c498ede87079a10b8e (patch)
tree45f501e484f81caed179adbe25613cf70dee3fd1
parent259cccd7e7faf23047b9fe9fb551f27c8fd4ee27 (diff)
soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50454 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/cezanne/fch.c23
-rw-r--r--src/soc/amd/cezanne/include/soc/southbridge.h4
2 files changed, 25 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index 5fb4f0ab98..3e2eadeb15 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -1,12 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpimmio.h>
+#include <amdblocks/smi.h>
#include <assert.h>
+#include <cpu/x86/smm.h>
#include <soc/iomap.h>
+#include <soc/smi.h>
#include <soc/southbridge.h>
static void fch_init_acpi_ports(void)
{
+ u32 reg;
+
/* We use some of these ports in SMM regardless of whether or not
* ACPI tables are generated. Enable these ports indiscriminately.
*/
@@ -17,8 +22,22 @@ static void fch_init_acpi_ports(void)
pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
if (CONFIG(HAVE_SMI_HANDLER)) {
- /* TODO: add code for SMI handler case */
- dead_code();
+ /* APMC - SMI Command Port */
+ pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
+ configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
+
+ /* SMI on SlpTyp requires sending SMI before completion
+ response of the I/O write. */
+ reg = pm_read32(PM_PCI_CTRL);
+ reg |= FORCE_SLPSTATE_RETRY;
+ pm_write32(PM_PCI_CTRL, reg);
+
+ /* Disable SlpTyp feature */
+ reg = pm_read8(PM_RST_CTRL1);
+ reg &= ~SLPTYPE_CONTROL_EN;
+ pm_write8(PM_RST_CTRL1, reg);
+
+ configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
} else {
pm_write16(PM_ACPI_SMI_CMD, 0);
}
diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h
index 9353e13ace..dcb5ef1872 100644
--- a/src/soc/amd/cezanne/include/soc/southbridge.h
+++ b/src/soc/amd/cezanne/include/soc/southbridge.h
@@ -6,6 +6,8 @@
#include <soc/iomap.h>
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
+#define PM_PCI_CTRL 0x08
+#define FORCE_SLPSTATE_RETRY BIT(25)
#define PWR_RESET_CFG 0x10
#define TOGGLE_ALL_PWR_GOOD (1 << 1)
#define PM_SERIRQ_CONF 0x54
@@ -50,6 +52,8 @@
#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29)
+#define PM_RST_CTRL1 0xbe
+#define SLPTYPE_CONTROL_EN BIT(5)
#define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1)