intel/gma: Don't bluntly enable I/O

The allocator should take care of this.

Change-Id: I4ec88ebe23b4dcab069f764decc8b9b0c6e6a142
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40726
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 11 insertions, 13 deletions

diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index e9bd722da9..b48b3c3100 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -154,7 +154,7 @@ static void gma_func0_init(struct device *dev)
 
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index ae9e25704d..fa67fe1982 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -464,7 +464,7 @@ static void gma_func0_init(struct device *dev)
 
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	/* Init graphics power management */
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 181aee56e7..71ed4c42ea 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -674,8 +674,7 @@ static void gma_func0_init(struct device *dev)
 
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER
-		 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
 
 	if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
 		int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
@@ -717,10 +716,9 @@ static void gma_func1_init(struct device *dev)
 	u32 reg32;
 	u8 val;
 
-	/* IGD needs to be Bus Master, also enable IO access */
+	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, reg32 |
-			PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
 
 	if (get_option(&val, "tft_brightness") == CB_SUCCESS)
 		pci_write_config8(dev, 0xf4, val);
diff --git a/src/northbridge/intel/ironlake/gma.c b/src/northbridge/intel/ironlake/gma.c
index 6de64fb065..6ba95d30fc 100644
--- a/src/northbridge/intel/ironlake/gma.c
+++ b/src/northbridge/intel/ironlake/gma.c
@@ -141,7 +141,7 @@ static void gma_func0_init(struct device *dev)
 
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index e2d0d18bad..7e5b236bff 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -224,7 +224,7 @@ static void gma_func0_init(struct device *dev)
 
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	if (!CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 82e43fc575..6e89b4ef35 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -591,7 +591,7 @@ static void gma_func0_init(struct device *dev)
 
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	/* Init graphics power management */
diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 004960fd8c..69b6f7103d 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -28,7 +28,7 @@ static void gma_func0_init(struct device *dev)
 
 	/* IGD needs to be Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	/* configure GMBUSFREQ */
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index fbd45cb7fe..0f83937a77 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -498,7 +498,7 @@ static void igd_init(struct device *dev)
 
 	/* IGD needs to be Bus Master */
 	u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 5110aad3d6..6b035bc736 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -47,7 +47,7 @@ static void gma_init(struct device *const dev)
 
 	/* IGD needs to Bus Master */
 	u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	reg32 |= PCI_COMMAND_MASTER;
 	pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {