Move MCP55_PCI_E_X_* to Kconfig. Any useless values in romstage.cs were

not brought over to Kconfig (this applies to all #defines to 4, as
that's the default anyway)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6104 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

18 files changed, 51 insertions, 41 deletions

diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig
index 4abe1c8744..7e7b169814 100644
--- a/src/mainboard/gigabyte/m57sli/Kconfig
+++ b/src/mainboard/gigabyte/m57sli/Kconfig
@@ -95,4 +95,8 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
+config MCP55_PCI_E_X_0
+	int
+	default 0
+
 endif # BOARD_GIGABYTE_M57SLI
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 7665c7b622..c50e15bdde 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -76,8 +76,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 	return smbus_read_byte(device, address);
 }
 
-#define MCP55_PCI_E_X_0 0
-
 #define MCP55_MB_SETUP \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig
index 4cfcc1749b..69964eafd0 100644
--- a/src/mainboard/msi/ms7260/Kconfig
+++ b/src/mainboard/msi/ms7260/Kconfig
@@ -93,4 +93,8 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
+config MCP55_PCI_E_X_0
+	int
+	default 0
+
 endif # BOARD_MSI_MS7260
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index 13dd4049b4..7da2361422 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -76,8 +76,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 #include "resourcemap.c"
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_PCI_E_X_0 0
-
 #define MCP55_MB_SETUP \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig
index 32d66edf2f..9df6a1413e 100644
--- a/src/mainboard/msi/ms9652_fam10/Kconfig
+++ b/src/mainboard/msi/ms9652_fam10/Kconfig
@@ -192,4 +192,8 @@ config HT3_SUPPORT
 	bool
 	default y
 
+config MCP55_PCI_E_X_0
+	int
+	default 1
+
 endif # BOARD_MSI_MS9652_FAM10
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 4ee1eebbb3..3d6bf3a966 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -78,8 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_PCI_E_X_0 1
-
 #define MCP55_MB_SETUP \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig
index 1dead70a42..5e76c30f5a 100644
--- a/src/mainboard/nvidia/l1_2pvv/Kconfig
+++ b/src/mainboard/nvidia/l1_2pvv/Kconfig
@@ -97,4 +97,8 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
+config MCP55_PCI_E_X_0
+	int
+	default 2
+
 endif # BOARD_NVIDIA_L1_2PVV
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index ed8e33a607..56b0855e4f 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -86,9 +86,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_PCI_E_X_0 2
-#define MCP55_PCI_E_X_1 4
-
 #define MCP55_MB_SETUP \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index 4f32816ebb..ecaa2f93e6 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -141,8 +141,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index eb5cc05c7a..dad1b9ea54 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -86,8 +86,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 16a7624212..34837f2cbf 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -79,8 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 885d06828f..5c0cab41ff 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -82,8 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_PCI_E_X_0 4
-
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig
index 4eadd39d1b..6258d93ea0 100644
--- a/src/mainboard/tyan/s2912/Kconfig
+++ b/src/mainboard/tyan/s2912/Kconfig
@@ -88,4 +88,8 @@ config IRQ_SLOT_COUNT
 	int
 	default 11
 
+config MCP55_PCI_E_X_0
+	int
+	default 1
+
 endif # BOARD_TYAN_S2912
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 745c00081a..39be36a240 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -86,8 +86,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/dualcore/dualcore.c"
 
-#define MCP55_PCI_E_X_0 1
-
 #define MCP55_MB_SETUP \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index a03176b2e3..30facb9782 100644
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -105,4 +105,8 @@ config HEAP_SIZE
 	hex
 	default 0xc0000
 
+config MCP55_PCI_E_X_0
+	int
+	default 1
+
 endif # BOARD_TYAN_S2912_FAM10
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index a3ffff902e..49bcd1af8b 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -79,8 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #include "cpu/amd/quadcore/quadcore.c"
 
-#define MCP55_PCI_E_X_0 1
-
 #define MCP55_MB_SETUP \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
 	RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig
index bbb5ab8ed3..78a1f254c5 100644
--- a/src/southbridge/nvidia/mcp55/Kconfig
+++ b/src/southbridge/nvidia/mcp55/Kconfig
@@ -3,26 +3,46 @@ config SOUTHBRIDGE_NVIDIA_MCP55
 	select HAVE_USBDEBUG
 	select IOAPIC
 
+if SOUTHBRIDGE_NVIDIA_MCP55
+
 config ID_SECTION_OFFSET
 	hex
-	default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55
+	default 0x80
 
 config EHCI_BAR
 	hex
-	default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55
+	default 0xfef00000
 
 config EHCI_DEBUG_OFFSET
 	hex
-	default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55
+	default 0x98
 
 config MCP55_USE_NIC
 	bool
-	default n if SOUTHBRIDGE_NVIDIA_MCP55
+	default n
 
 config MCP55_USE_AZA
 	bool
-	default n if SOUTHBRIDGE_NVIDIA_MCP55
+	default n
 
 config MCP55_NUM
 	int
-	default 1 if SOUTHBRIDGE_NVIDIA_MCP55
+	default 1
+
+config MCP55_PCI_E_X_0
+	int
+	default 4
+
+config MCP55_PCI_E_X_1
+	int
+	default 4
+
+config MCP55_PCI_E_X_2
+	int
+	default 4
+
+config MCP55_PCI_E_X_3
+	int
+	default 4
+
+endif
diff --git a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
index 773ad7154f..bf778a93fa 100644
--- a/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
@@ -76,19 +76,6 @@ static void setup_ss_table(unsigned index, unsigned where, unsigned control, con
 	 8 0 4 4 4 8 :5
 */
 
-#ifndef MCP55_PCI_E_X_0
-	#define MCP55_PCI_E_X_0	4
-#endif
-#ifndef MCP55_PCI_E_X_1
-	#define MCP55_PCI_E_X_1	4
-#endif
-#ifndef MCP55_PCI_E_X_2
-	#define MCP55_PCI_E_X_2	4
-#endif
-#ifndef MCP55_PCI_E_X_3
-	#define MCP55_PCI_E_X_3	4
-#endif
-
 #define MCP55_CHIP_REV	3
 
 static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
@@ -370,7 +357,7 @@ static int mcp55_early_setup_x(void)
 		FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation
 		Need to use same trick about pci1234 to verify node/link connection
 	*/
-	unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {MCP55_PCI_E_X_0, MCP55_PCI_E_X_1, MCP55_PCI_E_X_2, MCP55_PCI_E_X_3 };
+	unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3 };
 	int mcp55_num = 0;
 	unsigned busnx;
 	unsigned devnx;