diff options
| author | Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> | 2020-01-15 10:13:26 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-11 14:39:06 +0000 |
| commit | c34bb3807c9318742d7a1224a38bf03fda0c1723 (patch) | |
| tree | ca08a50cb09a4e1662a42b901753560c880a0de6 | |
| parent | 35d78437991a60882f52dcfe0f653966f10041ff (diff) | |
mb/google/volteer: Enable pcie rp11 for optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe
storage device and NVMe Optane memory. Storage device uses rp9 and
optane memory uses rp11. This patch enables rp11. Please note that
these two share clk related pins.
Configuring pciecontroller3 to be set from 2x2. This will by done by
auto detecting optane memory: enabling HybridStorageMode.
BUG=b:148604250
BRANCH=chromeos
TEST='Build, boot and look for two NVMe devices with lspci on Volteer'
Cq-Depend: chrome-internal:2501837
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: I5430829b496ed275e2e3bda3c0bf21c3d2132628
Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreboot-intel-private/jsl-tgl/+/2424428
Tested-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39420
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index b08ff7d5c9..a65e5f1be8 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -46,6 +46,10 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + # Enable Optane PCIE 11 using clk 0 + register "PcieRpEnable[10]" = "1" + register "HybridStorageMode" = "1" + # Enable SD Card PCIE 8 using clk 3 register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" @@ -311,7 +315,7 @@ chip soc/intel/tigerlake device pci 1d.0 on end # RP9 0xA0B0 device pci 1d.1 off end # RP10 0xA0B1 - device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 device pci 1d.4 off end # RP13 0xA0B4 device pci 1d.5 off end # RP14 0xA0B5 |