diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-14 06:58:39 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-20 21:38:54 +0000 |
| commit | c0733e1639bc97cd1774c556edd6bb6526876529 (patch) | |
| tree | 41bb4158f088aa89c05dc63fd3bdd6e9ae9fae4f | |
| parent | c92efa336397b917081706dabeb6f41cf69176e8 (diff) | |
ACPI: Use common OperationRegion for PCI_MMCONF
Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/acpi/dsdt_top.asl | 13 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/pci_int.asl | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl | 3 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/acpi/pci_int.asl | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/acpi/pcie.asl | 4 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/acpi/pci_int.asl | 4 |
6 files changed, 14 insertions, 18 deletions
diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index 160a53fc7b..eece7f7f22 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -32,9 +32,14 @@ Method (_PIC, 1) } #if CONFIG(MMCONF_SUPPORT) -/* Base address of PCIe config space */ -Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) +Scope(\_SB) { + /* Base address of PCIe config space */ + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) -/* Length of PCIe config space, 1MB each bus */ -Name(PCLN, CONFIG_MMCONF_LENGTH) + /* Length of PCIe config space, 1MB each bus */ + Name(PCLN, CONFIG_MMCONF_LENGTH) + + /* PCIe Configuration Space */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ +} #endif diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl index 0f1feef05a..e905c9738c 100644 --- a/src/soc/amd/stoneyridge/acpi/pci_int.asl +++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ - OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { + Field(PCFG, ByteAcc, NoLock, Preserve) { /* Byte offsets are computed using the following technique: * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 40e882c004..4580b772f0 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -284,8 +284,7 @@ Field( SMIC, ByteAcc, NoLock, Preserve) { PGA3, 8 , } -OperationRegion(FCFG, SystemMemory, PCBA, 0x01000000) -Field(FCFG, DwordAcc, NoLock, Preserve) +Field(PCFG, DwordAcc, NoLock, Preserve) { /* XHCI */ Offset(0x00080010), /* Base address */ diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl index 37b2333b29..6ff81cd66f 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ - OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { + Field(PCFG, ByteAcc, NoLock, Preserve) { /* Byte offsets are computed using the following technique: * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl index 65ac920efa..f69ba1db24 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -29,9 +29,7 @@ Scope(\) { } Scope(\_SB) { - /* PCIe Configuration Space for 16 busses */ - OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { + Field(PCFG, ByteAcc, NoLock, Preserve) { /* Byte offsets are computed using the following technique: * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space diff --git a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl index 37b2333b29..6ff81cd66f 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ - OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ - Field(PCFG, ByteAcc, NoLock, Preserve) { + Field(PCFG, ByteAcc, NoLock, Preserve) { /* Byte offsets are computed using the following technique: * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space |