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authorPatrick Rudolph <siro@das-labor.org>2017-09-30 09:13:53 +0200
committerMartin Roth <martinroth@google.com>2017-10-22 02:21:23 +0000
commitbb98b38b93d1f01fd3cd71c9e27ddbf4d3f1d244 (patch)
treeef23cb0b7639f8d22fc72a86b108441808a992ee
parent177f7731aa459e1171a7b118e884a40a90a5da60 (diff)
nb/intel/pineview: Port ACPI opregion to pineview
Port the ACPI opregion implementation that resides in drivers/intel/gma to older platforms. It allows to include a vbt.bin and allows GNU/Linux to load the opregion as ASLB is being set. Windows' Intel will likely ignore it as it relies on legacy VBIOS to be loaded at 0xc0000. Change-Id: Ifc9fc52d84dcbb0da577e61467ece8a48752f44b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/northbridge/intel/pineview/Kconfig1
-rw-r--r--src/northbridge/intel/pineview/gma.c51
2 files changed, 52 insertions, 0 deletions
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 1af8d3cb4c..e8ef9d9403 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -28,6 +28,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
select RELOCATABLE_RAMSTAGE
+ select INTEL_GMA_ACPI
config BOOTBLOCK_NORTHBRIDGE_INIT
string
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index c92428e36c..d47fc0eb89 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -31,6 +31,9 @@
#include "pineview.h"
#include <drivers/intel/gma/intel_bios.h>
#include <drivers/intel/gma/i915.h>
+#include <drivers/intel/gma/opregion.h>
+#include <southbridge/intel/i82801gx/nvs.h>
+#include <cbmem.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
@@ -55,6 +58,19 @@
static struct resource *gtt_res = NULL;
static struct resource *mmio_res = NULL;
+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+ const global_nvs_t *gnvs_ptr = gnvs;
+ return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
+}
+
+void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
+{
+ global_nvs_t *gnvs_ptr = gnvs;
+ if (gnvs_ptr)
+ gnvs_ptr->aslb = aslb;
+}
+
static int gtt_setup(u8 *mmiobase)
{
u32 gttbase;
@@ -278,6 +294,8 @@ static void gma_func0_init(struct device *dev)
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW");
}
+
+ intel_gma_restore_opregion();
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -303,6 +321,37 @@ const struct i915_gpu_controller_info *intel_gma_get_controller_info(void)
return &chip->gfx;
}
+static unsigned long
+gma_write_acpi_tables(struct device *const dev,
+ unsigned long current,
+ struct acpi_rsdp *const rsdp)
+{
+ igd_opregion_t *opregion = (igd_opregion_t *)current;
+ global_nvs_t *gnvs;
+
+ if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
+ return current;
+
+ current += sizeof(igd_opregion_t);
+
+ /* GNVS has been already set up */
+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
+ if (gnvs) {
+ /* IGD OpRegion Base Address */
+ gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
+ } else {
+ printk(BIOS_ERR, "Error: GNVS table not found.\n");
+ }
+
+ current = acpi_align_current(current);
+ return current;
+}
+
+static const char *gma_acpi_name(const struct device *dev)
+{
+ return "GFX0";
+}
+
static struct pci_operations gma_pci_ops = {
.set_subsystem = gma_set_subsystem,
};
@@ -316,6 +365,8 @@ static struct device_operations gma_func0_ops = {
.scan_bus = 0,
.enable = 0,
.ops_pci = &gma_pci_ops,
+ .acpi_name = gma_acpi_name,
+ .write_acpi_tables = gma_write_acpi_tables,
};
static const unsigned short pci_device_ids[] =