diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-05-26 18:33:22 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-07-21 22:57:49 +0000 |
| commit | b622d4b27b0ebff33cab63ff1ea52c285d68e028 (patch) | |
| tree | a3adeadccdb620e9d622d4a3373975bacbc2f9bb | |
| parent | f6b2e6f836d74b2b3c024230834651ff237fd884 (diff) | |
soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2
This patch performs below operations
1. Add support for FSP 2.2
2. Set EnableMultiPhaseSiliconInit to ensure bootloader can call
FspMultiPhaseSiInit() API.
3. Provide placeholder to perform require chipset programming (example TCSS)
before calling FspMultiPhaseSiInit() API.
Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params.c | 20 |
2 files changed, 21 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 091abb927f..51c379dff2 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -32,7 +32,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_1 + select PLATFORM_USES_FSP2_2 select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select SMP diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 798c16a425..cf24021841 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -327,9 +327,29 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } + /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ + params->EnableMultiPhaseSiliconInit = 1; mainboard_silicon_init_params(params); } +/* + * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit + * This platform supports below MultiPhaseSIInit Phase(s): + * Phase | FSP return point | Purpose + * ------- + ------------------------------------------------ + ------------------------------- + * 1 | After TCSS initialization completed | for TCSS specific init + */ +void platform_fsp_multi_phase_init_cb(uint32_t phase_index) +{ + switch (phase_index) { + case 1: + /* TCSS specific initialization here */ + break; + default: + break; + } +} + /* Mainboard GPIO Configuration */ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) { |