diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-28 08:32:21 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:48:30 +0100 |
| commit | ae1ef60dfa304450bacc475cd767ac4a610a76e0 (patch) | |
| tree | 6028ba70226a3c24838836429d765e6513329ffb | |
| parent | 116aa3a1900dae2beb56f381e91c9890c1e8ca30 (diff) | |
falco: Update DIMM SPD table
RAM_ID indices have been changed and settled on a 2GB config
that will be the same DRAM chips but only used in one channel.
Change-Id: I444e655883ae045622ab3dfb964da4d7f86e1c0d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56810
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4198
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
| -rw-r--r-- | src/mainboard/google/falco/Makefile.inc | 9 | ||||
| -rw-r--r-- | src/mainboard/google/falco/romstage.c | 6 |
2 files changed, 12 insertions, 3 deletions
diff --git a/src/mainboard/google/falco/Makefile.inc b/src/mainboard/google/falco/Makefile.inc index e19db11114..edb8cf602b 100644 --- a/src/mainboard/google/falco/Makefile.inc +++ b/src/mainboard/google/falco/Makefile.inc @@ -28,9 +28,12 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c SPD_BIN = $(obj)/spd.bin # Order of names in SPD_SOURCES is important! -SPD_SOURCES = Hynix_HMT425S6AFR6A -SPD_SOURCES += Micron_4KTF25664HZ -SPD_SOURCES += Elpida_EDJ4216EFBG +SPD_SOURCES = Micron_4KTF25664HZ # 4GB / CH0 + CH1 +SPD_SOURCES += Hynix_HMT425S6AFR6A # 4GB / CH0 + CH1 +SPD_SOURCES += Elpida_EDJ4216EFBG # 4GB / CH0 + CH1 +SPD_SOURCES += Micron_4KTF25664HZ # 2GB / CH0 only +SPD_SOURCES += Hynix_HMT425S6AFR6A # 2GB / CH0 only +SPD_SOURCES += Elpida_EDJ4216EFBG # 2GB / CH0 only SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 3bf1dbd300..ef6a849391 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -91,6 +91,12 @@ static void copy_spd(struct pei_data *peid) if (spd_file->len < sizeof(peid->spd_data[0])) die("Missing SPD data."); + /* Index 0-2 are 4GB config with both CH0 and CH1 + * Index 3-5 are 2GB config with CH0 only + */ + if (spd_index > 2) + peid->dimm_channel1_disabled = 3; + memcpy(peid->spd_data[0], ((char*)CBFS_SUBHEADER(spd_file)) + spd_index * sizeof(peid->spd_data[0]), |