diff options
| author | Anton Kochkov <anton.kochkov@gmail.com> | 2012-06-27 07:16:03 +0400 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2012-06-29 22:13:57 +0200 |
| commit | ac6e3172ff7c1c11da59c488b239d08af1248503 (patch) | |
| tree | c09f1ce7160f01029d299932adc410b2a7338e12 | |
| parent | 8fef6625050fc7973dab8c6d2ca317057bd978b2 (diff) | |
libpayload: OHCI driver correct PCI BAR reading
Correct registers base (PCI BAR) reading to be
more specification friendly. Registers base
only in [31-12] bits, all other proposed to be 0
but that not true for some motherboards. So
adding mask to use only valid bits.
Change-Id: I2e9a4997e016dab812ccfe654e966bc91d42a625
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1143
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | payloads/libpayload/drivers/usb/ohci.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 2e22ecf9e7..8a01cf24fb 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -111,7 +111,9 @@ ohci_init (pcidev_t addr) OHCI_INST (controller)->roothub = controller->devices[0]; controller->bus_address = addr; - controller->reg_base = pci_read_config32 (controller->bus_address, 0x10); // OHCI mandates MMIO, so bit 0 is clear + /* regarding OHCI spec, Appendix A, BAR_OCHI register description, Table A-4 + * BASE ADDRESS only [31-12] bits. All other usually 0, but not all */ + controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base); printf("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf); |