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authorTristan Corrick <tristan@corrick.kiwi>2018-12-26 23:46:27 +1300
committerPatrick Georgi <pgeorgi@google.com>2019-01-03 20:07:41 +0000
commita6fe456cb52c5133eb5e09d11dc83c0419b5692a (patch)
tree632d715752502ac836bb619a963ff7ebffe65389
parent68dc36c9b30f2ca48a199861bf450af3a6a0fd52 (diff)
Doc/nb/intel/haswell: Add a list of known issues
Change-Id: If0339831550f6c70e8056f78633e9a402f35a793 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30455 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--Documentation/mainboard/asrock/h81m-hds.md4
-rw-r--r--Documentation/northbridge/intel/haswell/index.md4
-rw-r--r--Documentation/northbridge/intel/haswell/known-issues.md28
3 files changed, 36 insertions, 0 deletions
diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md
index 460af8feaf..5e80f2b92c 100644
--- a/Documentation/mainboard/asrock/h81m-hds.md
+++ b/Documentation/mainboard/asrock/h81m-hds.md
@@ -78,6 +78,10 @@ facing towards the bottom of the board.
in coreboot. The `coretemp` driver can still be used for accurate CPU
temperature readings from an OS.
+```eval_rst
+Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
+```
+
## Untested
- parallel port
diff --git a/Documentation/northbridge/intel/haswell/index.md b/Documentation/northbridge/intel/haswell/index.md
index 3eb80594b8..87fb56f483 100644
--- a/Documentation/northbridge/intel/haswell/index.md
+++ b/Documentation/northbridge/intel/haswell/index.md
@@ -6,3 +6,7 @@ coreboot.
## Proprietary blobs
- [mrc.bin](mrc.bin.md)
+
+## Issues
+
+- [Known issues](known-issues.md)
diff --git a/Documentation/northbridge/intel/haswell/known-issues.md b/Documentation/northbridge/intel/haswell/known-issues.md
new file mode 100644
index 0000000000..c684b8fd65
--- /dev/null
+++ b/Documentation/northbridge/intel/haswell/known-issues.md
@@ -0,0 +1,28 @@
+# Known issues with Haswell
+
+These issues are specific to the Haswell architecture. For a given
+mainboard, there might be additional issues to those listed here.
+
+## PCIe graphics
+
+```eval_rst
+Using a PCIe graphics card for display output is not currently
+supported. This is because :doc:`./mrc.bin` requires workarounds to
+have such a feature working correctly.
+```
+
+However, there is a [patch on Gerrit][hsw-gfx-gerrit] that allows PCIe
+graphics to be used for display output. This patch is not guaranteed to
+be of the same level of quality as code committed to coreboot.
+
+Still, in some cases, a PCIe graphics card can be used for rendering,
+while the integrated graphics device is used for display output. This
+can be achieved under GNU/Linux by using [PRIME GPU offloading][PRIME].
+
+## PCIe 3.0
+
+Only PCIe 2.0 has been tested so far. PCIe 3.0 could potentially have
+stability issues.
+
+[PRIME]: https://wiki.archlinux.org/index.php/PRIME
+[hsw-gfx-gerrit]: https://review.coreboot.org/c/30456