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authorNico Huber <nico.huber@secunet.com>2017-07-24 17:09:35 +0200
committerNico Huber <nico.h@gmx.de>2017-07-27 13:56:45 +0000
commita67dd9de7708563df5b7f019b3c32ac005d5db2e (patch)
treea39887796f57437832158350df61cd6583891812
parent812f1783bbf437e57e7176ec8a2d29e478c27e92 (diff)
libpayload/storage: Enable bus mastering for AHCI
This is (thankfully) not done by coreboot any more for recent chipsets. Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--payloads/libpayload/drivers/storage/ahci.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c
index 0e7fd7d8e0..3a0b99df42 100644
--- a/payloads/libpayload/drivers/storage/ahci.c
+++ b/payloads/libpayload/drivers/storage/ahci.c
@@ -34,6 +34,7 @@
#include <string.h>
#include <libpayload.h>
#include <pci.h>
+#include <pci/pci.h>
#include <storage/ata.h>
#include <storage/ahci.h>
@@ -267,6 +268,10 @@ static void ahci_init_pci(pcidev_t dev)
/* Set AHCI access mode. */
ctrl->global_ctrl |= HBA_CTRL_AHCI_EN;
+ /* Enable bus mastering. */
+ const u16 command = pci_read_config16(dev, PCI_COMMAND);
+ pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER);
+
/* Probe for devices. */
for (i = 0; i < 32; ++i) {
if (ctrl->ports_impl & (1 << i))