summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorStephen Douthit <stephend@silicom-usa.com>2019-08-05 10:46:02 -0400
committerPatrick Georgi <pgeorgi@google.com>2020-03-10 20:45:34 +0000
commita51f4908704bee5e83f911eaf2fc241795b060ac (patch)
tree261b7afa9bb391274301c036670623d10219ad11
parentaa6a8fb9198acfe22fec944bc9484a800d689ff4 (diff)
soc/intel/dnv: Fix ACPI reporting of root port interrupt routing
pcie_port.asl defines an IRQM method that looks up legacy interrupt swizzling based on incoming interrupt "pin" A-D and root port number. Unfortunately the 8-bit root port number stored at offset 0x4F in the config space matches the device number, not the 1-8 scheme used in the LUT reported to the OS. Fix the case values to match the hardware. Change-Id: I103d632a4bc99461f02e05aa0f9a9eb7376770d9 Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34712 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/soc/intel/denverton_ns/acpi/pcie.asl16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/denverton_ns/acpi/pcie.asl b/src/soc/intel/denverton_ns/acpi/pcie.asl
index cb14cf8bb3..c9bbd3fa80 100644
--- a/src/soc/intel/denverton_ns/acpi/pcie.asl
+++ b/src/soc/intel/denverton_ns/acpi/pcie.asl
@@ -120,7 +120,7 @@ Method (IRQM, 1, Serialized) {
Switch (ToInteger (Arg0)) {
/* PCIe Root Port 1 */
- Case (Package() { 1 }) {
+ Case (Package() { 9 }) {
If (PICM) {
Return (IQAA)
} Else {
@@ -129,7 +129,7 @@ Method (IRQM, 1, Serialized) {
}
/* PCIe Root Port 2 */
- Case (Package() { 2 }) {
+ Case (Package() { 10 }) {
If (PICM) {
Return (IQBA)
} Else {
@@ -138,7 +138,7 @@ Method (IRQM, 1, Serialized) {
}
/* PCIe Root Port 3 */
- Case (Package() { 3 }) {
+ Case (Package() { 11 }) {
If (PICM) {
Return (IQCA)
} Else {
@@ -147,7 +147,7 @@ Method (IRQM, 1, Serialized) {
}
/* PCIe Root Port 4 */
- Case (Package() { 4 }) {
+ Case (Package() { 12 }) {
If (PICM) {
Return (IQDA)
} Else {
@@ -156,7 +156,7 @@ Method (IRQM, 1, Serialized) {
}
/* PCIe Root Port 5 */
- Case (Package() { 5 }) {
+ Case (Package() { 14 }) {
If (PICM) {
Return (IQEA)
} Else {
@@ -165,7 +165,7 @@ Method (IRQM, 1, Serialized) {
}
/* PCIe Root Port 6 */
- Case (Package() { 6 }) {
+ Case (Package() { 15 }) {
If (PICM) {
Return (IQFA)
} Else {
@@ -174,7 +174,7 @@ Method (IRQM, 1, Serialized) {
}
/* PCIe Root Port 7 */
- Case (Package() { 7 }) {
+ Case (Package() { 16 }) {
If (PICM) {
Return (IQGA)
} Else {
@@ -183,7 +183,7 @@ Method (IRQM, 1, Serialized) {
}
/* PCIe Root Port 8 */
- Case (Package() { 8 }) {
+ Case (Package() { 17 }) {
If (PICM) {
Return (IQHA)
} Else {