diff options
| author | Matt DeVillier <matt.devillier@puri.sm> | 2019-06-15 16:42:00 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-06-28 19:11:03 +0000 |
| commit | 85d3b40a19358c4014eceaea3204feece8b15edd (patch) | |
| tree | 0542a1debf5d4fed418337d18702461b2c332b8e | |
| parent | 16a70c3d40db0d31d8b6c6c13603d27ad6bf5be3 (diff) | |
soc/intel/cannonlake: fix use of legacy 8254 timer
FSP sets the use of the 8254 timer via the Enable8254ClockGating
UPD, which defaults to enabled, overriding what is set by coreboot.
Per the FSP integration guide, this UPD needs to be disabled when
a legacy OS is booted (ie, when SeaBIOS is used as the payload).
Add a Kconfig option to set the UPD properly based on payload
selection, and remove the existing coreboot code in lpc.c since
it is either ineffective or being overridden by FSP.
Test: build/boot out-of-tree WHL board with both SeaBIOS and
Tianocore, ensure 8254 timer usage set correctly for each.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/lpc.c | 11 |
4 files changed, 12 insertions, 13 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 2279df2247..679efce396 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -314,4 +314,12 @@ config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. +config USE_LEGACY_8254_TIMER + bool "Use Legacy 8254 Timer" + default y if PAYLOAD_SEABIOS + default n + help + This sets the Enable8254ClockGating UPD, which according to the FSP Integration + guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled. + endif diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3b4c980e2d..71aa2086d5 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -246,8 +246,6 @@ struct soc_intel_cannonlake_config { /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; - /* Statically clock gate 8254 PIT. */ - uint8_t clock_gate_8254; /* Enable C6 DRAM */ uint8_t enable_c6dram; /* diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dd9388296d..783ebb7ab3 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -244,6 +244,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 56fefa5c05..6cc34515d7 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -207,16 +207,6 @@ static void pch_misc_init(void) outb(0x70, (1 << 7)); }; -static void clock_gate_8254(const struct device *dev) -{ - const config_t *config = dev->chip_info; - - if (!config->clock_gate_8254) - return; - - itss_clock_gate_8254(); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -237,7 +227,6 @@ void lpc_soc_init(struct device *dev) soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); - clock_gate_8254(dev); soc_mirror_dmi_pcr_io_dec(); } |