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authorDuncan Laurie <dlaurie@chromium.org>2015-09-04 13:53:14 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-09-10 09:47:57 +0000
commit7fce30c2a5dd748ab3efa79fb24e3c85cef11628 (patch)
tree12ff4714796da2da3dfd1cb5574df66d443fb8f2
parentc1bc8171e65bb9100c4e9cb0efe8e5aa9771d4d3 (diff)
skylake: Enable DPTF based on devicetree setting
Enable DPTF flag in ACPI NVS based on devicetree setting for the mainboard. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glaods coreboot Change-Id: I06ec6b050eb83c6a7ee1e48f2bd9f5920f7bfa51 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5728a8a37b1a50a483aa211563fb7ad312002ce5 Original-Change-Id: I08d61416c24b3c8857205cf88931f0bb2b38896c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297755 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/soc/intel/skylake/acpi.c6
-rw-r--r--src/soc/intel/skylake/chip.h3
2 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 87d4eb0707..1c3ec792ae 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -169,6 +169,9 @@ static int get_cores_per_package(void)
void acpi_init_gnvs(global_nvs_t *gnvs)
{
+ const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ const struct soc_intel_skylake_config *config = dev->chip_info;
+
/* Set unknown wake source */
gnvs->pm1i = -1;
@@ -189,6 +192,9 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
#endif
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
#endif
+
+ /* Enable DPTF based on mainboard configuration */
+ gnvs->dpte = config->dptf_enable;
}
unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 9b43b7fa2d..94aa3a4ea9 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -86,6 +86,9 @@ struct soc_intel_skylake_config {
/* Enable S0iX support */
int s0ix_enable;
+ /* Enable DPTF support */
+ int dptf_enable;
+
/* Deep SX enable for both AC and DC */
int deep_s3_enable;
int deep_s5_enable;