diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2018-04-08 15:05:12 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-04-11 14:18:35 +0000 |
| commit | 73cd7cf0f28d77a9a4afe56ca0e0a9485b2eae48 (patch) | |
| tree | 663da369409a6ef89d480f6ca99846862ab96c07 | |
| parent | f42c7d9670302bac9119f0473e4283882960ffbb (diff) | |
src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)
Fixes: 2269a3c328 ("soc/amd/stoneyridge: Add functions for GPIO interrupts")
Change-Id: I5730259bc6819defc482d31644e1f476679257b2
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25588
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/kahlee/bootblock/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/gpio.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 1eb18f1667..641287c1bd 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -39,7 +39,7 @@ void bootblock_mainboard_init(void) /* Configure cr50 interrupt pin for use in polling tpm status */ if (IS_ENABLED(CONFIG_MAINBOARD_HAS_TPM_CR50)) { - const uint32_t flags = GPIO_EDGEL_TRIG | GPIO_ACTIVE_LOW | + const uint32_t flags = GPIO_EDGE_TRIG | GPIO_ACTIVE_LOW | GPIO_INT_STATUS_EN; gpio_set_interrupt(H1_PCH_INT, flags); } diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 2c3555b8ea..e1ae5dda09 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -23,7 +23,7 @@ #include <soc/iomap.h> #include <types.h> -#define GPIO_EDGEL_TRIG (0 << 8) +#define GPIO_EDGE_TRIG (0 << 8) #define GPIO_LEVEL_TRIG (1 << 8) #define GPIO_TRIGGER_MASK (1 << 8) |