diff options
| author | Barnali Sarkar <barnali.sarkar@intel.com> | 2017-02-03 13:28:46 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-08 20:04:17 +0100 |
| commit | 6ff7e8f550df1ef05e93546892888b66c132ae31 (patch) | |
| tree | 8ef9be8ab6cda44a5c545ef53ad6b9a083dbf78a | |
| parent | 0254c2d99fc7a5858be4826c576ca743d005b213 (diff) | |
vendorcode/intel/skykabylake: Update CpuConfigFspData.h file
The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.
Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18285
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h index 8fd41e07d7..c8cdc5fd27 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h @@ -62,9 +62,9 @@ typedef union { UINT32 TxtEnable : 1; UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0. UINT32 RsvdBits : 15; ///< Reserved for future use - EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor. + UINT32 Reserved; } Bits; - UINT32 Uint32[3]; + UINT32 Uint32[2]; } CPU_CONFIG_FSP_DATA; #pragma pack (pop) |