diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-09 17:45:27 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-05-14 22:26:24 +0000 |
commit | 6f7e8dee588de6f425c27a8271e2cdcb8075deeb (patch) | |
tree | 5384054d1cfa2e56d91efdf39fa0581b3ea46812 | |
parent | 9749a85cb0aea99818a7b0047cbb04fa0a60e07c (diff) |
nb/intel/fsp_sandybridge: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
-rw-r--r-- | src/northbridge/intel/fsp_sandybridge/acpi.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/fsp_sandybridge/gma.c | 7 | ||||
-rw-r--r-- | src/northbridge/intel/fsp_sandybridge/northbridge.c | 17 |
3 files changed, 14 insertions, 12 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c index 28df4a5151..842277117f 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ b/src/northbridge/intel/fsp_sandybridge/acpi.c @@ -23,7 +23,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - device_t dev; + struct device *dev; u32 pciexbar = 0; u32 pciexbar_reg; int max_buses; diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c index 1433a01165..2cfd1f3e70 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.c +++ b/src/northbridge/intel/fsp_sandybridge/gma.c @@ -66,7 +66,8 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) gnvs_ptr->aslb = aslb; } -static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void gma_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -80,7 +81,7 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) const struct i915_gpu_controller_info * intel_gma_get_controller_info(void) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); if (!dev) { return NULL; } @@ -88,7 +89,7 @@ intel_gma_get_controller_info(void) return &chip->gfx; } -static void gma_ssdt(device_t device) +static void gma_ssdt(struct device *device) { const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); if (!gfx) { diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 2dfe44d84e..3a07d42a6c 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -63,7 +63,7 @@ static const int legacy_hole_size_k = 384; static int get_pcie_bar(u32 *base) { - device_t dev; + struct device *dev; u32 pciexbar_reg; *base = 0; @@ -99,7 +99,7 @@ static void add_fixed_resources(struct device *dev, int index) mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } -static void pci_domain_set_resources(device_t dev) +static void pci_domain_set_resources(struct device *dev) { uint64_t tom, me_base, touud; uint32_t tseg_base, uma_size, tolud; @@ -235,7 +235,7 @@ static struct device_operations pci_domain_ops = { .scan_bus = pci_domain_scan_bus, }; -static void mc_read_resources(device_t dev) +static void mc_read_resources(struct device *dev) { u32 pcie_config_base; int buses; @@ -249,7 +249,8 @@ static void mc_read_resources(device_t dev) } } -static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void intel_set_subsystem(struct device *dev, unsigned vendor, + unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -274,7 +275,7 @@ static void northbridge_init(struct device *dev) printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); } -static u32 northbridge_get_base_reg(device_t dev, int reg) +static u32 northbridge_get_base_reg(struct device *dev, int reg) { u32 value; @@ -286,7 +287,7 @@ static u32 northbridge_get_base_reg(device_t dev, int reg) u32 northbridge_get_tseg_base(void) { - const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); return northbridge_get_base_reg(dev, TSEG); } @@ -328,7 +329,7 @@ static const struct pci_driver mc_driver_1 __pci_driver = { .device = 0x0154, /* Ivy bridge */ }; -static void cpu_bus_init(device_t dev) +static void cpu_bus_init(struct device *dev) { initialize_cpus(dev->link_list); } @@ -341,7 +342,7 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; -static void enable_dev(device_t dev) +static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { |