soc/intel/baytrail: Use a variable for s3resume

This helps towards unified chipset_power_state.

Change-Id: I532384ad6c5b2e793ed70f31763f2c8873443816
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

1 files changed, 4 insertions, 2 deletions

diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index e9513cd8ec..dbf4afc17a 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -108,12 +108,14 @@ void mainboard_romstage_entry(void)
 
 	printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
 
-	elog_boot_notify(prev_sleep_state == ACPI_S3);
+	int s3resume = prev_sleep_state == ACPI_S3;
+
+	elog_boot_notify(s3resume);
 
 	/* Initialize RAM */
 	raminit(&mp, prev_sleep_state);
 
 	timestamp_add_now(TS_AFTER_INITRAM);
 
-	romstage_handoff_init(prev_sleep_state == ACPI_S3);
+	romstage_handoff_init(s3resume);
 }