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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-13 16:12:47 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-14 19:21:03 +0000 |
| commit | 6962b6ecd395093e63824bb337bbb45492d2ce48 (patch) | |
| tree | c97afe898d55407458f0dc1fd3b81bbc9b225710 | |
| parent | aed4aca3fcc7209224229b813b353cc78ae0e0ed (diff) | |
sb,soc/amd: Move _PIC method to global scope
Fix regression with commit aa969e887a ACPI: Move PICM declaration.
While mentioned in the commit message there already, the default
value for AMD boards changed from IOAPIC mode to PIC mode.
ACPI 6.3 spec has this text regarding _PIC method:
If the platform CPU architecture supports PIC mode and the method
is never called, the platform runtime firmware must assume PIC mode.
If MADT has IOAPIC entries, OS will want to change to APIC model. But
the method _PIC was not in the global scope so it could not be called
and therefore _PRT continued to report PIC model interrupt routing.
Already fixed for soc/amd/picasso in commit 839f668.
Change-Id: I7f3bb0d45946cec315694de1d540fea4d828348e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/amd/stoneyridge/acpi/pci_int.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/acpi/pci_int.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/acpi/pcie.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/acpi/pci_int.asl | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/pci_int.asl b/src/soc/amd/stoneyridge/acpi/pci_int.asl index ae7665522c..e7fc96d77a 100644 --- a/src/soc/amd/stoneyridge/acpi/pci_int.asl +++ b/src/soc/amd/stoneyridge/acpi/pci_int.asl @@ -103,7 +103,7 @@ P3PR, 1, } - Method(_PIC, 0x01, NotSerialized) + Method(\_PIC, 0x01, NotSerialized) { If (Arg0) { diff --git a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl index a01fb5b700..8fc5b4dd32 100644 --- a/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/agesa/hudson/acpi/pci_int.asl @@ -103,7 +103,7 @@ P3PR, 1, } - Method(_PIC, 0x01, NotSerialized) + Method(\_PIC, 0x01, NotSerialized) { If (Arg0) { diff --git a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl index a154fd80e0..3d32e32e00 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/pcie.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/pcie.asl @@ -132,7 +132,7 @@ Scope(\_SB) { P3PR, 1, } - Method(_PIC, 0x01, NotSerialized) + Method(\_PIC, 0x01, NotSerialized) { If (Arg0) { diff --git a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl index a01fb5b700..8fc5b4dd32 100644 --- a/src/southbridge/amd/pi/hudson/acpi/pci_int.asl +++ b/src/southbridge/amd/pi/hudson/acpi/pci_int.asl @@ -103,7 +103,7 @@ P3PR, 1, } - Method(_PIC, 0x01, NotSerialized) + Method(\_PIC, 0x01, NotSerialized) { If (Arg0) { |