diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-12-18 01:17:08 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-12-19 03:14:50 +0000 |
| commit | 5e9ba6e3b42927d88222731b62436788e72b3ec4 (patch) | |
| tree | cddfde867d8bba245f70a070b46f95b473b1d312 | |
| parent | 2d12a901fbbb4cc5ee5255616cd9960223c310e0 (diff) | |
mb/google/poppy: Configure GPP_B0 for WLAN wake
As per the latest schematics, this change configures GPP_B0 for WLAN
wake and uses corresponding gpe bit in ACPI node for WLAN. This hasn't
been tested yet.
BUG=b:70775494
Change-Id: I5198b8083a87d00f890b45986e5e3f62b81686c2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22928
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/poppy/variants/baseboard/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/google/poppy/variants/baseboard/gpio.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index ceb0c95a0e..2ddf22a948 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -355,7 +355,7 @@ chip soc/intel/skylake device pci 19.2 on end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" + register "wake" = "GPE0_DW0_00" device pci 00.0 on end end end # PCI Express Port 1 diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index d0e2097b0d..4dcecef62b 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -62,8 +62,8 @@ static const struct pad_config gpio_table[] = { /* A23 : ISH_GP5 ==> NC */ PAD_CFG_NC(GPP_A23), - /* B0 : CORE_VID0 ==> NC(TP42) */ - PAD_CFG_NC(GPP_B0), + /* B0 : CORE_VID0 ==> WLAN_PCIE_WAKE_L */ + PAD_CFG_GPI_ACPI_SCI(GPP_B0, NONE, DEEP, INVERT), /* B1 : CORE_VID1 ==> NC(TP43) */ PAD_CFG_NC(GPP_B1), /* B2 : VRALERT# ==> NC */ |