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| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-10-07 13:17:09 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:35:51 +0000 |
| commit | 54e1f59215f3adb6ab1f2e8f2413a71ae7a545c2 (patch) | |
| tree | 6fd8042f825e5b1e9a374c773bec9cf83e097eae | |
| parent | 7f6335324bb80d9a06bc9832a4fcc3726d74976f (diff) | |
sb/intel/lynxpoint: Set PCIe L1 substates capabilities register
Copied from soc/intel/broadwell.
Test: build/boot google/beltino variants, verify L1 PM substates
listed under PCIe device capabilities
Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46134
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 077dcd6573..2da14ed5f0 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -676,6 +676,12 @@ static void pch_pcie_early(struct device *dev) else pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29)); + /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); + else + pci_update_config32(dev, 0x200, ~0xfffff, 0); + if (is_lp) pci_or_config32(dev, 0x100, 1 << 29); |